Table of Contents

• Chip Design in the Era of AI & Quantum: From Idea to IC, are we there yet?Leon Stok. 1 [doi]
• Technology-Aware 3D Placement with ILP-Based Region Planning for Soft ModulesCheng-Xun Song, Minh Anh Phan, Sheng-Tan Huang, Shao-Yun Fang, Tung-Chieh Chen, Kai-Shun Hu, Cindy Chin-Fang Shen. 2-10 [doi]
• IDDA-3D: Inter-Die Delay Aware Timing-Driven Placement on Face-to-Face Bonded 3D ICsZixian Yang, Shanyi Li, Leilei Jin, Tsung-Yi Ho, Chien-Nan Jimmy Liu. 11-19 [doi]
• Multi-Level Interconnect Planning for Signal-Power-Thermal Integrity in 2.5D/3D IntegrationSiyuan Miao, Lingkang Zhu, Xiangqiao Meng, Wenkai Yang, Chengyu Zhu, Chen Wu, Lei He 0001. 20-28 [doi]
• LiDAR 3.0: Photonics-Aware Planning-Guided Automated Electrical Routing for Large-Scale Active Photonic Integrated CircuitsHongjian Zhou, Haoyu Yang, Nicholas Gangi, Bowen Liu, Meng Zhang 0023, Haoxing Ren, Xu Wang, Rena Huang, Jiaqi Gu 0002. 29-37 [doi]
• Invited: Navigating the Frontier of Optimality and Complexity: Advanced Design Automation for Wavelength-Routed ONoCsZhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann. 38-45 [doi]
• Any-Angle Die-to-Die Routing for Advanced Packages with Asymmetric Pin Row Structures, Via Constraints, and Shielding-Aware ReservationHsin-Tzu Chang, Iris Hui-Ru Jiang, Hua-Yu Chang, Chun-Hao Lai. 46-54 [doi]
• Gradient-Guided RC Weighting for Timing-Driven Global RoutingLiang Xiao 0001, Qinkai Duan, Leilei Jin, Jinwei Liu, Tsung-Yi Ho, Evangeline F. Y. Young, Martin D. F. Wong. 55-63 [doi]
• GrandPlan: Differentiable, Simultaneous Top-Level Floorplanning and Partition-Level Cell Placement for Large-Scale IP-CoresZhili Xiong, Yi-Chen Lu, David Z. Pan, Haoxing Ren. 64-72 [doi]
• Invited: BonnRoute: Classic Routing Algorithms with Recent AdvancesJens Vygen. 73-74 [doi]
• A Graph-Based Approach for Optimizing Pin Access in Nanosheet FET Standard Cell Library SynthesisMeng-Yu Shih, Ting Xin Lin, Yih-Lang Li. 75-82 [doi]
• TransOpt: A Scalable Transistor-Level Placement and Routing Optimization Framework Beyond Standard CellsChen-Hao Hsu, David Z. Pan. 83-91 [doi]
• A New Approach to Performance-Driven Analog IC PlacementDonghao Fang, Hailiang Hu, Wuxi Li, Jiang Hu 0001. 92-100 [doi]
• Physical Synthesis/layout Issues Specific to FPGA-based EmulationHelena Krupnova. 101-108 [doi]
• How Optical Lithography Enables the Digital AgeThomas Stammler. 109 [doi]
• Invited: Agentic Chip Design from Spec2GDS - Faster and Better than a Human Expert?Thomas Andersen. 110-111 [doi]
• Invited: Infusing EDA Knowledge into LLM Systems: An Information-Source PerspectiveYuhan Qin, Yuan Pu 0001, Tairu Qiu, Zhuolun He, Bei Yu 0001. 112-120 [doi]
• Invited: Polymath: Self-Improving Hierarchical Workflow for Multi-Domain Problem SolvingChia-Tung Ho, Jing Gong, Haoyu Yang, Abhishek B. Akkur, Haoxing Ren. 121-130 [doi]
• Invited: Breaking through Chip Design Barriers with AI-powered Physical Design MethodologiesAnkur Gupta. 131-132 [doi]
• Invited: Agentic AI for Physical Design R&D: Status and ProspectsAmur Ghose, Andrew B. Kahng, Sayak Kundu, Bodhisatta Pramanik. 133-141 [doi]
• Use of AI/ML in Electronic Design Automation and Engineering SimulationPrith Banerjee. 142-143 [doi]
• AstroTune: AST-Assisted LLM Retrieval for Cross-Stage Design Flow Parameter TunerRunzhi Wang 0005, Jingyu Pan, Yiran Chen 0001, Jiang Hu 0001. 144-152 [doi]
• CHASE: A CHiplet Architecture Simulation and Exploration Framework with Decoupled Multi-Fidelity OptimizationShixin Chen, Hengyuan Zhang, Jianwang Zhai, Bei Yu 0001. 153-161 [doi]
• Invited: A Bidirectional EDA Flow in VLSI Design Using Ontology and Knowledge GraphIlhami H. Torunoglu. 162 [doi]
• Invited: Improving Runtime Scaling in the EDA Flow for Designs with Millions of GatesDavid G. Chinnery. 163-171 [doi]
• Invited: Challenges and Opportunities in Advanced-node Design ClosureWill Reece. 172 [doi]
• An Improved Ion-Shuttling Approach for QCCD ArchitecturesTung-Yeh Wu, Ting-Chi Wang. 173-181 [doi]
• Timing-Aware End-to-End Circuit Compilation Framework for Modular Quantum SystemsChing-Yao Huang, Wai-Kei Mak. 182-190 [doi]
• Invited: Toward Accurate, Large-scale Electromigration Analysis and Optimization in Integrated SystemsSachin S. Sapatnekar. 191-199 [doi]
• Invited: Electromigration Avoidance Strategies in InfineonShanthi Siemes. 200 [doi]
• Invited: Addressing Electromigration Challenges in 3D Integrated Circuit (3DIC) Wafer-On-Wafer Technology: EM analysis in 3DIC - status and challengesIngo Kühn, Ivan Valentinov Petkov. 201-202 [doi]
• Invited: Substrate Netlist Extraction in Analog DesignKlaus Heinrich, Pietro Buccella. 203-204 [doi]
• Invited: Novel Concepts to Improve Custom Layout Automation CapabilitiesGöran Jerke, Thomas Burdick, Vinko Marolt, Peter Herth, Andrew Beckett. 205-213 [doi]
• Invited: Analog Computation with Oscillatory Neural NetworksAida Todri-Sanial. 214-215 [doi]
• Invited: Analog IC Design Automation - More than a Technical ChallengeBenjamin Prautsch, Uwe Eichler. 216-217 [doi]
• Invited: A History of InfluencesJürgen Scheible. 218-219 [doi]
• Invited: The Many PD Faces of Professor Jens LienigAndrew B. Kahng. 220-225 [doi]
• Invited: From Evolutionary Algorithms to Analog Design, Electromigration, 3D Integration, and Beyond: On Jens Lienig's Contributions to Advance Physical DesignJohann Knechtel, Susann Rothe, Robert Fischbach, Matthias Thiele, Tilo Meister, Andreas Krinke. 226-235 [doi]
• Invited: Layout Design Automation: From Academia to Industry and BackJens Lienig. 236 [doi]
• Studying the Brain from the Perspective of EELouis K. Scheffer. 237 [doi]
• Invited: Benchmarker: A Web-Based System for Tracking Experimental ResultsRahul Rana, Tejas Bachhav, Aniruddha Dhumal, Ashutosh Pareek, Riya Sara Angel Korrapolu, Sathya Sai Ram Prabhala, Dishant Bhatnagar, Patrick H. Madden. 238-244 [doi]
• Invited: Toward Sustainable and Transparent Benchmarking for Academic Physical Design ResearchLiwen Jiang, Andrew B. Kahng, Zhiang Wang, Zhiyu Zheng. 245-253 [doi]
• Invited: Modern Hypergraph Partitioning: KaHyPar, Mt-KaHyPar, and BeyondSebastian Schlag, Tobias Heuer, Christian Schulz 0003. 254-255 [doi]
• Invited: Post-Placement Buffering and Sizing ContestAndrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Yiting Liu 0002, Davit Markarian, SeongHyeon Park, Zhiang Wang. 256-262 [doi]