Abstract is missing.
- System prototypes: virtual, hardware or hybrid?Tom Borgstrom, Eshel Haritan, Ron Wilson, David Abada, Andrew Dauman, Ramesh Chandra, Olivier Mielo, Chuck Cruse, Achim Nohl. 1-3 [doi]
- Circuit techniques for dynamic variation toleranceKeith A. Bowman, James Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar. 4-7 [doi]
- Enabling adaptability through elastic clocksEmre Tuncer, Jordi Cortadella, Luciano Lavagno. 8-10 [doi]
- Addressing design margins through error-tolerant circuitsShidhartha Das, David Blaauw, David Bull, Krisztián Flautner, Rob Aitken. 11-12 [doi]
- Worst-case aggressor-victim alignment with current-source driver modelsRavikishore Gandikota, Li Ding 0002, Peivand Tehrani, David Blaauw. 13-18 [doi]
- A moment-based effective characterization waveform for static timing analysisDavid D. Ling, Chandu Visweswariah, Peter Feldmann, Soroush Abbaspour. 19-24 [doi]
- A false-path aware formal static timing analyzer considering simultaneous input transitionsShihheng Tsai, Chung-Yang Huang. 25-30 [doi]
- Way Stealing: cache-assisted automatic instruction set extensionsTheo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon. 31-36 [doi]
- SysCOLA: a framework for co-development of automotive software and system platformZhonglei Wang, Andreas Herkersdorf, Wolfgang Haberl, Martin Wechs. 37-42 [doi]
- Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysisMichael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty. 43-46 [doi]
- Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gatingJungseob Lee, Nam Sung Kim. 47-50 [doi]
- Design automation for a 3DIC FFT processor for synthetic aperture radar: a case studyThorlindur Thorolfsson, Kiran Gonsalves, Paul D. Franzon. 51-56 [doi]
- Selective wordline voltage boosting for caches to manage yield under process variationsYan Pan, Joonho Kong, Serkan Ozdemir, Gokhan Memik, Sung Woo Chung. 57-62 [doi]
- Double patterning lithography friendly detailed routing with redundant via considerationKun Yuan, Katrina Lu, David Z. Pan. 63-66 [doi]
- Use of lithography simulation for the calibration of equation-based design rule checksDavid Abercrombie, Fedor Pikus, Cosmin Cazan. 67-70 [doi]
- Carbon nanotube circuits in the presence of carbon nanotube density variationsJie Zhang, Nishant Patil, Arash Hazeghi, Subhasish Mitra. 71-76 [doi]
- Decoding nanowire arrays fabricated with the multi-spacer patterning techniqueM. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De Micheli. 77-82 [doi]
- Boolean logic function synthesis for generalised threshold gate circuitsMarek A. Bawiec, Maciej Nikodem. 83-86 [doi]
- Improving STT MRAM storage density through smaller-than-worst-case transistor sizingWei Xu, Yiran Chen, XiaoBin Wang, Tong Zhang. 87-90 [doi]
- EDA in flux: should I stay or should I go?Eshel Haritan, Andreas Kuehlmann, Tina Jones, John Epperheimer, Jan M. Rabaey, Rahul Razdan, Naveen Gupta. 91-92 [doi]
- Design perspectives on 22nm CMOS and beyondShekhar Borkar. 93-94 [doi]
- Creating an affordable 22nm node using design-lithography co-optimizationAndrzej J. Strojwas, T. Jhaveri, V. Rovner, Lawrence T. Pileggi. 95-96 [doi]
- Device/circuit interactions at 22nm technology nodeKaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta. 97-102 [doi]
- Beyond innovation: dealing with the risks and complexity of processor design in 22nmCarl J. Anderson. 103 [doi]
- Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variabilityLerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He. 104-109 [doi]
- A Gaussian mixture model for statistical timing analysisShingo Takahashi, Yuki Yoshida, Shuji Tsukiyama. 110-115 [doi]
- A stochastic jitter model for analyzing digital timing-recovery circuitsJames R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi. 116-121 [doi]
- Statistical ordering of correlated timing quantities and its application for path rankingJinjun Xiong, Chandu Visweswariah, Vladimir Zolotov. 122-125 [doi]
- A parametric approach for handling local variation effects in timing analysisAyhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik. 126-129 [doi]
- Non-intrusive dynamic application profiling for multitasked applicationsKarthik Shankar, Roman L. Lysecky. 130-135 [doi]
- A trace-capable instruction cache for cost efficient real-time program trace compression in SoCChun-Hung Lai, Fu-Ching Yang, Chung-Fu Kao, Ing-Jer Huang. 136-141 [doi]
- Generating test programs to cover pipeline interactionsThanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra. 142-147 [doi]
- NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-coreChi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Alan Peisheng Su. 148-153 [doi]
- Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependenceVineeth Veetil, Dennis Sylvester, David Blaauw, Saumil Shah, Steffen Rochel. 154-159 [doi]
- Resurrecting infeasible clock-gating functionsEli Arbel, Cindy Eisner, Oleg Rokhlenko. 160-165 [doi]
- Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communicationsRenshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng. 166-171 [doi]
- ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC modelsCedric Walravens, Yves Vanderperren, Wim Dehaene. 172-177 [doi]
- GPU friendly fast Poisson solver for structured power grid network analysisJin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon X.-D. Tan, Pei-Hsin Ho, Xiaoyi Wang. 178-183 [doi]
- Fast vectorless power grid verification using an approximate inverse techniqueNahi H. Abdul Ghani, Farid N. Najm. 184-189 [doi]
- Computing bounds for fault tolerance using formal techniquesGörschwin Fey, André Sülflow, Rolf Drechsler. 190-195 [doi]
- Clock skew optimization via wiresizing for timing sign-off covering all process cornersSari Onaissi, Khaled R. Heloue, Farid N. Najm. 196-201 [doi]
- Moore s Law: another casualty of the financial meltdown?Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork. 202-203 [doi]
- Holistic verification: myth or magic bullet?Pradip A. Thaker. 204-208 [doi]
- Verification problems in reusing internal design componentsWarren Stapleton, Paul Tobin. 209-211 [doi]
- Exploiting architecture for verification to streamline the verification processDave Whipp. 212-215 [doi]
- An efficient approach for system-level timing simulation of compiler-optimized embedded softwareZhonglei Wang, Andreas Herkersdorf. 220-225 [doi]
- MPTLsim: a simulator for X86 multicore processorsHui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry V. Ponomarev. 226-231 [doi]
- Trace-driven workload simulation method for Multiprocessor System-On-ChipsTsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Toshio Isomura, Kazuo Satou. 232-237 [doi]
- Analysis and mitigation of process variation impacts on Power-Attack ToleranceLang Lin, Wayne P. Burleson. 238-243 [doi]
- Evaluating design trade-offs in customizable processorsUnmesh D. Bordoloi, Huynh Phung Huynh, Samarjit Chakraborty, Tulika Mitra. 244-249 [doi]
- A design flow for application specific heterogeneous pipelined multiprocessor systemsHaris Javaid, Sri Parameswaran. 250-253 [doi]
- Xquasher: a tool for efficient computation of multiple linear expressionsArash Arfaee, Ali Irturk, Nikolay Laptev, Farzan Fallah, Ryan Kastner. 254-257 [doi]
- ILP-based pin-count aware design methodology for microfluidic biochipsCliff Chiung-Yu Lin, Yao-Wen Chang. 258-263 [doi]
- O-Router: an optical routing framework for low power on-chip silicon nano-photonic integrationDuo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, David Z. Pan. 264-269 [doi]
- BDD-based synthesis of reversible logic for large functionsRobert Wille, Rolf Drechsler. 270-275 [doi]
- Soft connections: addressing the hardware-design modularity problemMichael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer. 276-281 [doi]
- A computing origami: folding streams in FPGAsAndrei Hagiescu, Weng-Fai Wong, David F. Bacon, Rodric M. Rabbah. 282-287 [doi]
- Retiming and recycling for elastic systems with early evaluationDmitry Bufistov, Jordi Cortadella, Marc Galceran Oms, Jorge Júlvez, Michael Kishinevsky. 288-291 [doi]
- Speculation in elastic systemsMarc Galceran Oms, Jordi Cortadella, Michael Kishinevsky. 292-295 [doi]
- DFM: don t care or competitive weapon?Mark Redford, Joseph Sawicki, Prasad Subramaniam, Cliff Hou, Yervant Zorian, Kimon Michaels. 296-297 [doi]
- The semiconductor industry s nanoelectronics research initiative: motivation and challengesJeff Welser. 298-300 [doi]
- Single-electron devices for ubiquitous and secure computing applicationsKen Uchida. 301-303 [doi]
- Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questionsNishant Patil, Albert Lin, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra. 304-309 [doi]
- An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree constructionChih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Yao-Hsin Chou. 314-319 [doi]
- GRIP: scalable 3D global routing using integer programmingTai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth. 320-325 [doi]
- Automatic bus planner for dense PCBsHui Kong, Tan Yan, Martin D. F. Wong. 326-331 [doi]
- A correct network flow model for escape routingTan Yan, Martin D. F. Wong. 332-335 [doi]
- Flip-chip routing with unified area-I/O pad assignments for package-board co-designJia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang. 336-339 [doi]
- Statistical multilayer process space coverage for at-speed testJinjun Xiong, Yiyu Shi, Vladimir Zolotov, Chandu Visweswariah. 340-345 [doi]
- Speedpath analysis based on hypothesis pruning and rankingNicholas Callegari, Li-C. Wang, Pouria Bastani. 346-351 [doi]
- Interconnection fabric design for tracing signals in post-silicon validationXiao Liu, Qiang Xu. 352-357 [doi]
- Online cache state dumping for processor debugAnant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan. 358-363 [doi]
- Finding deterministic solution from underdetermined equation: large-scale performance modeling by least angle regressionXin Li. 364-369 [doi]
- A robust and efficient harmonic balance (HB) using direct solution of HB JacobianAmit Mehrotra, Abhishek Somani. 370-375 [doi]
- Stochastic steady-state and AC analyses of mixed-signal systemsJaeha Kim, Jihong Ren, Mark A. Horowitz. 376-381 [doi]
- Parallelizable stable explicit numerical integration for efficient circuit simulationWei Dong, Peng Li. 382-385 [doi]
- Efficient design-specific worst-case corner extraction for integrated circuitsHong Zhang, Tsung-Hao Chen, Ming Yuan Ting, Xin Li. 386-389 [doi]
- Timing-driven optimization using lookahead logic circuitsMihir R. Choudhury, Kartik Mohanram. 390-395 [doi]
- Simulation and SAT-based Boolean matching for large Boolean networksKuo-Hua Wang, Chung-Ming Chan, Jung-Chang Liu. 396-401 [doi]
- New spare cell design for IR drop minimization in Engineering Change OrderHsien-Te Chen, Chieh-Chun Chang, TingTing Hwang. 402-407 [doi]
- Matching-based minimum-cost spare cell selection for design changesIris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung. 408-411 [doi]
- Handling don t-care conditions in high-level synthesis and application for reducing initialized registersHong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo. 412-415 [doi]
- Oil fields, hedge funds, and drugsPatrick Groeneveld, Rob A. Rutenbar, Jed W. Pitera, Erik C. Carlson, Jinsong Chen. 416-417 [doi]
- Human computationLuis von Ahn. 418-419 [doi]
- How to make computers that work like the brainDileep George. 420-423 [doi]
- A fully polynomial time approximation scheme for timing driven minimum cost buffer insertionShiyan Hu, Zhuo Li, Charles J. Alpert. 424-429 [doi]
- Spare-cell-aware multilevel analytical placementZhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao. 430-435 [doi]
- Handling complexities in modern large-scale mixed-size placementJackey Z. Yan, Natarajan Viswanathan, Chris Chu. 436-441 [doi]
- RegPlace: a high quality open-source placement framework for structured ASICsAshutosh Chakraborty, Anurag Kumar, David Z. Pan. 442-447 [doi]
- A novel verification technique to uncover out-of-order DUV behaviorsGabriel Marcilio, Luiz C. V. dos Santos, Bruno Albertini, Sandro Rigo. 448-453 [doi]
- Shortening the verification cycle with synthesizable abstract modelsAlon Gluska, Lior Libis. 454-459 [doi]
- Non-cycle-accurate sequential equivalence checkingPankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol Mathur, Nikhil Sharma. 460-465 [doi]
- Regression verificationBenny Godlin, Ofer Strichman. 466-471 [doi]
- Accurate temperature estimation using noisy thermal sensorsYufu Zhang, Ankur Srivastava. 472-477 [doi]
- Spectral techniques for high-resolution thermal characterization with limited sensor dataRyan Cochran, Sherief Reda. 478-483 [doi]
- Dynamic thermal management via architectural adaptationRamkumar Jayaseelan, Tulika Mitra. 484-489 [doi]
- On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency considerationMin Bao, Alexandru Andrei, Petru Eles, Zebo Peng. 490-495 [doi]
- SRAM parametric failure analysisJian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi. 496-501 [doi]
- Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithmWeiguang Sheng, Liyi Xiao, Zhigang Mao. 502-507 [doi]
- Improving testability and soft-error resilience through retimingSmita Krishnaswamy, Igor L. Markov, John P. Hayes. 508-513 [doi]
- Statistical reliability analysis under process variation and aging effectsYinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng. 514-519 [doi]
- Guess, solder, measure, repeat: how do I get my mixed-signal chip right?Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O Leary, Sandeep Tare, Warren Wong. 520-521 [doi]
- The Cilk++ concurrency platformCharles E. Leiserson. 522-527 [doi]
- Misleading performance claims in parallel computationsDavid H. Bailey. 528-533 [doi]
- Massively parallel processing: it s déjà vu all over againSteven P. Levitan, Donald M. Chiarulli. 534-538 [doi]
- Provably good and practically efficient algorithms for CMP dummy fillChunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng. 539-544 [doi]
- Predicting variability in nanoscale lithography processesDragoljub Gagi Drmanac, Frank Liu, Li-C. Wang. 545-550 [doi]
- Variability analysis under layout pattern-dependent rapid-thermal annealing processYun Ye, Frank Liu, Min Chen, Yu Cao. 551-556 [doi]
- Event-driven gate-level simulation with GP-GPUsDebapriya Chatterjee, Andrew DeOrio, Valeria Bertacco. 557-562 [doi]
- Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cutsHimanshu Jain, Edmund M. Clarke. 563-568 [doi]
- Constraints in one-to-many concretization for abstraction refinementKuntal Nanshi, Fabio Somenzi. 569-574 [doi]
- Spectrum: a hybrid nanophotonic-electric on-chip networkZheng Li, Dan Fay, Alan R. Mickelson, Li Shang, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun. 575-580 [doi]
- Exploring serial vertical interconnects for 3D ICsSudeep Pasricha. 581-586 [doi]
- No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chipsShu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang. 587-592 [doi]
- Thermal-driven analog placement considering device matchingPo-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang. 593-598 [doi]
- Yield-driven iterative robust circuit optimization algorithmYan Li, Vladimir Stojanovic. 599-604 [doi]
- Contract-based system-level composition of analog circuitsXuening Sun, Pierluigi Nuzzo, Chang-Ching Wu, Alberto L. Sangiovanni-Vincentelli. 605-610 [doi]
- Serial reconfigurable mismatch-tolerant clock distributionAtanu Chattopadhyay, Zeljko Zilic. 611-612 [doi]
- Thermal-aware data flow analysisJosé Luis Ayala, David Atienza, Philip Brisk. 613-614 [doi]
- Nanoscale digital computation through percolationMustafa Altun, Marc D. Riedel, Claudia Neuhauser. 615-616 [doi]
- A learning digital computerBo Marr, Arindam Basu, Stephen Brink, Paul E. Hasler. 617-618 [doi]
- Programmable neural processing on a smartdustShimeng Huang, Joseph Oresko, Yuwen Sun, Allen C. Cheng. 619-620 [doi]
- Human computing for EDAAndrew DeOrio, Valeria Bertacco. 621-622 [doi]
- Synthesizing hardware from sketchesAndreas Raabe, Rastislav BodÃk. 623-624 [doi]
- Endosymbiotic computing: enabling surrogate GUI and cyber-physical connectivityPai H. Chou. 625-626 [doi]
- Debugging from high level down to gate levelMasahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi. 627-630 [doi]
- The day Sherlock Holmes decided to do EDAAndreas G. Veneris, Sean Safarpour. 631-634 [doi]
- Debugging strategies for mere mortalsValeria Bertacco. 635-638 [doi]
- MAGENTA: transaction-based statistical micro-architectural root-cause analysisGila Kamhi, Alexander Novakovsky, Andreas Tiemeyer, Adriana Wolffberg. 639-643 [doi]
- Untwist your brain: efficient debugging and diagnosis of complex assertionsMichael Siegel, Adriana Maggiore, Christian Pichler. 644-647 [doi]
- Beyond verification: leveraging formal for debuggingRajeev K. Ranjan, Claudionor Coelho, Sebastian Skalberg. 648-651 [doi]
- Power modeling of graphical user interfaces on OLED displaysMian Dong, Yung-Seok Kevin Choi, Lin Zhong. 652-657 [doi]
- Energy-aware error control coding for Flash memoriesVeera Papirla, Chaitali Chakrabarti. 658-663 [doi]
- PDRAM: a hybrid PRAM and DRAM main memory systemGaurav Dhiman, Raid Ayoub, Tajana Rosing. 664-469 [doi]
- A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processorsIk Joon Chang, Debabrata Mohapatra, Kaushik Roy. 670-675 [doi]
- A physical unclonable function defined using power distribution system equivalent resistance variationsRyan Helinski, Dhruva Acharyya, Jim Plusquellic. 676-681 [doi]
- Hardware authentication leveraging performance limits in detailed simulations and emulationsDaniel Y. Deng, Andrew H. Chan, G. Edward Suh. 682-687 [doi]
- Hardware Trojan horse detection using gate-level characterizationMiodrag Potkonjak, Ani Nahapetian, Michael Nelson, Tammara Massey. 688-693 [doi]
- Process variation characterization of chip-level multiprocessorsLide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph. 694-697 [doi]
- Information hiding for trusted system designJunjun Gu, Gang Qu, Qiang Zhou. 698-701 [doi]
- On systematic illegal state identification for pseudo-functional testingFeng Yuan, Qiang Xu. 702-707 [doi]
- Automated failure population creation for validating integrated circuit diagnosis methodsWing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton. 708-713 [doi]
- Fault models for embedded-DRAM macrosMango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin. 714-719 [doi]
- Adaptive test elimination for analog/RF circuitsEnder Yilmaz, Sule Ozev. 720-725 [doi]
- WCET-aware register allocation based on graph coloringHeiko Falk. 726-731 [doi]
- Optimal static WCET-aware scratchpad allocation of program codeHeiko Falk, Jan C. Kleinsorge. 732-737 [doi]
- A real-time program trace compressor utilizing double move-to-front methodVladimir Uzelac, Aleksandar Milenkovic. 738-743 [doi]
- Heterogeneous code cache: using scratchpad and main memory in dynamic binary translatorsJosé Baiocchi, Bruce R. Childers. 744-749 [doi]
- From milliwatts to megawatts: system level power challengeRuchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach. 750-751 [doi]
- A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extractionWenwen Chai, Dan Jiao, Cheng-Kok Koh. 752-757 [doi]
- Variational capacitance extraction of on-chip interconnects based on continuous surface modelWenjian Yu, Chao Hu, Wangyang Zhang. 758-763 [doi]
- PiCAP: a parallel and incremental capacitance extraction considering stochastic process variationFang Gong, Hao Yu, Lei He. 764-769 [doi]
- An efficient resistance sensitivity extraction algorithm for conductors of arbitrary shapesTarek A. El-Moselhy, Ibrahim M. Elfadel, Bill Dewey. 770-775 [doi]
- Throughput optimal task allocation under thermal constraints for multi-core processorsVinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha. 776-781 [doi]
- An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systemsShaobo Liu, Qing Wu, Qinru Qiu. 782-787 [doi]
- Software-assisted hardware reliability: abstracting circuit-level challenges to the software stackVijay Janapa Reddi, Simone Campanoni, Meeta Sharma Gupta, Michael D. Smith, Gu-Yeon Wei, David M. Brooks. 788-793 [doi]
- Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimizationHochang Jang, Taewhan Kim. 794-799 [doi]
- An SDRAM-aware router for Networks-on-ChipWooyoung Jang, David Z. Pan. 800-805 [doi]
- Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiencyJun-hee Yoo, Sungjoo Yoo, Kiyoung Choi. 806-811 [doi]
- Vicis: a reliable network for unreliable siliconDavid Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester. 812-817 [doi]
- Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspectiveSiddharth Garg, Diana Marculescu, Radu Marculescu, Ãœmit Y. Ogras. 818-821 [doi]
- NoC topology synthesis for supporting shutdown of voltage islands in SoCsCiprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli. 822-825 [doi]
- Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systemsYoonjin Kim, Rabi N. Mahapatra. 826-831 [doi]
- Multicore parallel min-cost flow algorithm for CAD applicationsYinghai Lu, Hai Zhou, Li Shang, Xuan Zeng. 832-837 [doi]
- FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimationScott Cromar, Jaeho Lee, Deming Chen. 838-843 [doi]
- FPGA-based accelerator for the verification of leading-edge wireless systemsAmirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn. 844-847 [doi]
- Transmuting coprocessors: dynamic loading of FPGA coprocessorsChen Huang, Frank Vahid. 848-851 [doi]
- Dynamic thread and data mapping for NoC based CMPsMahmut T. Kandemir, Ozcan Ozturk, Sai Prashanth Muralidhara. 852-857 [doi]
- A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systemsYuan-Hao Chang, Tei-Wei Kuo. 858-863 [doi]
- Quality-driven synthesis of embedded multi-mode control systemsSoheil Samii, Petru Eles, Zebo Peng, Anton Cervin. 864-869 [doi]
- Context-sensitive timing analysis of Esterel programsLei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abhik Roychoudhury. 870-873 [doi]
- Scheduling the FlexRay bus using optimization techniquesHaibo Zeng, Wei Zheng, Marco Di Natale, Arkadeb Ghosal, Paolo Giusto, Alberto L. Sangiovanni-Vincentelli. 874-877 [doi]
- The wild west: conquest of complex hardware-dependent software designHiroyuki Yagi, Wolfgang Rosenstiel, Jakob Engblom, Jason Andrews, Kees A. Vissers, Marc Serughetti. 878-879 [doi]
- Internet-in-a-Box: emulating datacenter network architectures using FPGAsJonathan D. Ellithorpe, Zhangxi Tan, Randy H. Katz. 880-883 [doi]
- Sustainable data centers: enabled by supply and demand side managementPrith Banerjee, Chandrakant D. Patel, Cullen Bash, Parthasarathy Ranganathan. 884-887 [doi]
- Green data centers and hot chipsDilip D. Kandlur, Tom W. Keller. 888-890 [doi]
- Optimum LDPC decoder: a memory architecture problemErick Amador, Renaud Pacalet, Vincent Rezard. 891-896 [doi]
- A DVS-based pipelined reconfigurable instruction memoryZhiguo Ge, Tulika Mitra, Weng-Fai Wong. 897-902 [doi]
- LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processorsTalal Bonny, Jörg Henkel. 903-906 [doi]
- Hierarchical architecture of flash-based storage systems for high performance and durabilitySanghyuk Jung, Jin-Hyuk Kim, Yong Ho Song. 907-910 [doi]
- Reduction techniques for synchronous dataflow graphsMarc Geilen. 911-916 [doi]
- A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time managementHamid Shojaei, Amir Hossein Ghamarian, Twan Basten, Marc Geilen, Sander Stuijk, Rob Hoes. 917-922 [doi]
- Mode grouping for more effective generalized scheduling of dynamic dataflow applicationsWilliam Plishker, Nimish Sane, Shuvra S. Bhattacharyya. 923-926 [doi]
- Efficient program scheduling for heterogeneous multi-core processorsJian Chen, Lizy Kurian John. 927-930 [doi]
- Polynomial datapath optimization using partitioning and compensation heuristicsO. Sarbishei, Bijan Alizadeh, Masahiro Fujita. 931-936 [doi]
- Register allocation for high-level synthesis using dual supply voltagesInsup Shin, Seungwhun Paik, Youngsoo Shin. 937-942 [doi]
- GPU-based parallelization for fast circuit optimizationYifang Liu, Jiang Hu. 943-946 [doi]
- Architectural assessment of design techniques to improve speed and robustness in embedded microprocessorsThomas Baumann, Doris Schmitt-Landsiedel, Christian Pacha. 947-950 [doi]
- ARMS - automatic residue-minimization based sampling for multi-point modeling techniquesJorge Fernandez Villena, Luis Miguel Silveira. 951-956 [doi]
- An efficient passivity test for descriptor systems via canonical projector techniquesN. Wong. 957-962 [doi]
- A parameterized mask model for lithography simulationZhenhai Zhu. 963-968 [doi]