GÃ¶rschwin Fey - researchr alias

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Viewing Publication 1 - 7 from 7

2009

Effiziente ErfÃ¼llbarkeitsalgorithmen fÃ¼r die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation)Rolf Drechsler, Stephan EggersglÃ¼ÃŸ, GÃ¶rschwin Fey, JÃ¼rgen SchlÃ¶ffel, Daniel Tille. it, 51(2):102-111, 2009. [doi]

Computing bounds for fault tolerance using formal techniquesGÃ¶rschwin Fey, AndrÃ© SÃ¼lflow, Rolf Drechsler. dac 2009: 190-195 [doi]

Robustness Check for Multiple Faults Using Formal TechniquesStefan Frehse, GÃ¶rschwin Fey, AndrÃ© SÃ¼lflow, Rolf Drechsler. dsd 2009: 85-90 [doi]

Increasing the accuracy of SAT-based debuggingAndrÃ© SÃ¼lflow, GÃ¶rschwin Fey, CÃ©cile Braunstein, Ulrich KÃ¼hne, Rolf Drechsler. date 2009: 1326-1331 [doi]

Evaluation of Cardinality Constraints on SMT-Based DebuggingAndrÃ© SÃ¼lflow, Robert Wille, GÃ¶rschwin Fey, Rolf Drechsler. ismvl 2009: 298-303 [doi]

WoLFram- A Word Level Framework for Formal VerificationAndrÃ© SÃ¼lflow, Ulrich KÃ¼hne, GÃ¶rschwin Fey, Daniel GroÃŸe, Rolf Drechsler. rsp 2009: 11-17 [doi]

2008

Identifying a Subset of System Verilog Assertions for Efficient Bounded Model CheckingRobert Wille, GÃ¶rschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler. dsd 2008: 542-549 [doi]

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