Abstract is missing.
- An Experimental Model-Based Rapid Prototyping Environment for High-Confidence Embedded SoftwareJoseph Porter, Péter Völgyesi, Nicholas Kottenstette, Harmon Nine, Gabor Karsai, Janos Sztipanovits. 3-10 [doi]
- WoLFram- A Word Level Framework for Formal VerificationAndré Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler. 11-17 [doi]
- Rapid-Prototyping of Adaptive Component-Based Systems Using Runtime Aspectual InteractionsNasreddine Aoumeur, Kamel Barkaoui, Gunter Saake. 18-25 [doi]
- Adapting Models to Model Checkers, A Case Study : Analysing AADL Using Time or Colored Petri NetsXavier Renault, Fabrice Kordon, Jérôme Hugues. 26-33 [doi]
- A Formal Method for Rapid SoC PrototypingChristos Pavlatos, Alexandros C. Dimopoulos, George K. Papakonstantinou. 34-37 [doi]
- A Flexible High Throughput FPGA Based Prototype Platform for RW Channel DevelopmentBhasker Jakka, Dillip Dash, Caner Yalcin, Ly Dang, Omar Mire, Aldo Cometti. 41-47 [doi]
- Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-ChipsAlexandre Chagoya-Garzon, Xavier Guerin, Frédéric Rousseau, Frédéric Pétrot, Davide Rossetti, Alessandro Lonardo, Piero Vicini, Pier Stanislao Paolucci. 48-54 [doi]
- Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC PlatformsAmit Kumar Singh, Wu Jigang, Alok Prakash, Thambipillai Srikanthan. 55-60 [doi]
- Communication-Aware Hierarchical Online-Placement in Heterogeneous Reconfigurable SystemsSven Schneider, André Meisel, Wolfram Hardt. 61-67 [doi]
- Testing of an FPGA Based C2X-Communication Prototype with a Model Based Traffic GenerationOliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser. 68-71 [doi]
- Operating System Support for Difference-Based Partial Hardware ReconfigurationTiago de Albuquerque Reis, Antônio Augusto Fröhlich. 75-80 [doi]
- A Methodology for Rapid Optimization of HandelC SpecificationsJoseph C. Libby, Kenneth B. Kent. 81-87 [doi]
- High-Level System Modeling for Rapid HW/SW Architecture ExplorationChafic Jaber, Andreas Kanstein, Ludovic Apvrille, Amer Baghdadi, Patricia Le Moenner, Renaud Pacalet. 88-94 [doi]
- Rapid Prototyping Projection Algorithms with FPGA TechnologyJohn Cole, Larry Garey, Kenneth B. Kent. 95-101 [doi]
- Automatic Code Generation from Real-Time Systems SpecificationsLaura Carnevali, Dario D Amico, Lorenzo Ridi, Enrico Vicario. 102-105 [doi]
- Generating an Efficient Instruction Set Simulator from a Complete Property SuiteUlrich Kühne, Sven Beyer, Christian Pichler. 109-115 [doi]
- A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCsNicolas Pouillon, Alexandre Becoulet, Aline Vieira de Mello, François Pêcheux, Alain Greiner. 116-122 [doi]
- Configuration Measurement for FPGA-based Trusted PlatformsBenjamin Glas, Alexander Klimm, Klaus D. Müller-Glaser, Jürgen Becker. 123-129 [doi]
- Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear EqualizerAtif Raza Jafri, Amer Baghdadi, Michel Jézéquel. 130-133 [doi]
- High-Performance Buffer Mapping to Exploit DRAM Concurrency in Multiprocessor DSP SystemsDongwon Lee, Shuvra S. Bhattacharyya, Wayne Wolf. 137-144 [doi]
- Area-Time Estimation of Controller for Porting C-Based Functions onto FPGALieu My Chuong, Siew Kei Lam, Thambipillai Srikanthan. 145-151 [doi]
- Instruction Cache Tuning for Embedded Multitasking ApplicationsSantanu Kumar Dash, Thambipillai Srikanthan. 152-158 [doi]
- Efficient Data Access Management for FPGA-Based Image Processing SoCsZahir Larabi, Yves Mathieu, Stéphane Mancini. 159-165 [doi]
- Design and Implementation of an UWB Digital Transmitter Based on the Multiband OFDM Physical Layer ProposalMichalis Platsis, Ioannis Papaefstathiou, Dimitrios Meintanis. 166-169 [doi]
- Physical Layer Extraction of FlexRay Configuration ParametersMatthias Heinz, Verena Hoss, Klaus D. Müller-Glaser. 173-180 [doi]
- An Interactive Approach to Timing Accurate PCI-X SimulationKevin Andryc, Russell Tessier, Patrick Kelly. 181-187 [doi]
- An Approach to Supply Simulations of the Functional Environment of ECUs for Hardware-in-the-Loop Test Systems Based on EE-architectures Conform to AUTOSARMartin Hillenbrand, Klaus D. Müller-Glaser. 188-195 [doi]
- FPGA-based Radar Signal Processing for Automotive Driver Assistance SystemJean Saad, Amer Baghdadi, Frantz Bodereau. 196-199 [doi]