Table of Contents

• Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation PlatformAbdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur Senouci, Frédéric Pétrot. 3-9 [doi]
• Network Interface Sharing Techniques for Area Optimized NoC ArchitecturesAlberto Ferrante, Simone Medardoni, Davide Bertozzi. 10-17 [doi]
• Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty LinksDario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania. 18-25 [doi]
• CART: Communication-Aware Routing Technique for Application-Specific NoCsRafael Tornero, Juan Manuel Ordñua, Andres Mejia, Jose Flich, José Duato. 26-31 [doi]
• LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow ControlSergio Saponara, Francesco Vitullo, Riccardo Locatelli, Philippe Teninge, Marcello Coppola, Luca Fanucci. 32-35 [doi]
• Flexible Baseband Architectures for Future Wireless SystemsNajam-ul-Islam Muhammad, Rizwan Rasheed, Renaud Pacalet, Raymond Knopp, Karim Khalfallah. 39-46 [doi]
• A Lightweight Operating Environment for Next Generation Cognitive RadiosIsmael Gómez, Vuk Marojevic, José Salazar, Antoni Gelonch. 47-52 [doi]
• On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on ChipRuimin Huang, Niklas Lotze, Yiannos Manoli. 53-60 [doi]
• A Reconfigurable LFSR for Tri-standard SDR Transceiver, Architecture and Complexity AnalysisLaurent Alaus, Dominique Noguet, Jacques Palicot. 61-67 [doi]
• Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time SystemsViacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng. 71-80 [doi]
• Digital Systems Architectures Based on On-line CheckersMartin Straka, Zdenek Kotásek, Jan Winter. 81-87 [doi]
• Fault Models and Injection Strategies in SystemC SpecificationsCristiana Bolchini, Antonio Miele, Donatella Sciuto. 88-95 [doi]
• An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGAPetr Fiser, Pavel Kubalík, Hana Kubatova. 96-99 [doi]
• Experimental SEU Impact on Digital Design Implemented in FPGAsJirí Kvasnicka, Pavel Kubalík, Hana Kubatova. 100-103 [doi]
• Temperature and Leakage Aware Power Control for Embedded Streaming ApplicationsAndrea Alimonda, Andrea Acquaviva, Salvatore Carta. 107-114 [doi]
• Source-Level Estimation of Energy Consumption and Execution Time of Embedded SoftwareCarlo Brandolese. 115-123 [doi]
• Embedded Multicore Implementation of a H.264 Decoder with Power Management ConsiderationsSebastien Bilavarn, Cécile Belleudy, Michel Auguin, T. Dupont, Anne-Marie Fouilliart. 124-130 [doi]
• A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-ChipsMarkus Winter 0002, Gerhard Fettweis. 133-140 [doi]
• A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode SwitchingSimone Secchi, Francesca Palumbo, Danilo Pani, Luigi Raffo. 141-148 [doi]
• A Look-Ahead Task Management Unit for Embedded Multi-Core ArchitecturesMagnus Själander, Andrei Terechko, Marc Duranton. 149-157 [doi]
• A Modular Approach to Model Heterogeneous MPSoC at Cycle LevelMatteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa. 158-164 [doi]
• Performance and Timing Yield Enhancement using Highway-on-Chip PlanningAli Jahanian, Morteza Saheb Zamani. 165-172 [doi]
• An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router FailuresThomas Sødring, Ã…shild Grønstad Solheim, Tor Skeie, Sven-Arne Reinemo. 173-178 [doi]
• Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing UnitsNuno Sebastiao, Tiago Dias, Nuno Roma, Paulo F. Flores, Leonel Sousa. 181-188 [doi]
• Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core ArchitectureRoberto Giorgi, Zdravko Popovic, Nikola Puzovic, Arnaldo Azevedo, Ben H. H. Juurlink. 189-194 [doi]
• Design of a Two Dimensional PRSI Image ProcessorTheja Tulabandhula, Amit Patra, Nirmal B. Chakrabarti. 195-202 [doi]
• A Hardware Design for Camera-Based Power Management of Computer MonitorVasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu. 203-209 [doi]
• Co-design and Implementation of the H.264/AVC Motion Estimation Algorithm Using Co-simulationRoderick R. Colenbrander, Arjen S. Damstra, C. Wim Korevaar, C. A. Verhaar, Albert Molderink. 210-215 [doi]
• A Low-Cost Cache Coherence Verification Method for Snooping SystemsDemid Borodin, Ben H. H. Juurlink. 219-227 [doi]
• Dependability Evaluation of Real Railway Interlocking DeviceRadek Dobias, Jan Konarski, Hana Kubatova. 228-233 [doi]
• Formulating MITF for a Multicore Processor with SEU ToleranceToshimasa Funaki, Toshinori Sato. 234-241 [doi]
• Mapping a Fault-Tolerant Distributed Algorithm to Systems on ChipGottfried Fuchs, Matthias Függer, Ulrich Schmid, Andreas Steininger. 242-249 [doi]
• Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAsAndrzej Krasniewski. 250-255 [doi]
• Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm TechnologyAndrea Marongiu, Luca Benini, Andrea Acquaviva, Andrea Bartolini. 259-266 [doi]
• Restricted Chaining and Fragmentation Techniques in Power Aware High Level SynthesisAlberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida. 267-273 [doi]
• Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template SizingBehnam Ghavami, Mehrshad Khosraviani, Hossein Pedram. 274-281 [doi]
• Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?Sudip Roy, Ajit Pal. 282-289 [doi]
• Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis OptimizationsSharareh Zamanzadeh, Mohammad Mirza-Aghatabar, Mehrdad Najibi, Hossein Pedram, Abolghasem Sadeghi. 290-297 [doi]
• Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS CircuitsEnrico Macii, Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino. 298-303 [doi]
• Leveraging Data Promotion for Low Power D-NUCA CachesAlessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström. 307-316 [doi]
• Revisiting the Cache Effect on Multicore Multithreaded Network ProcessorsZhen Liu, Jia Yu, Xiaojun Wang, Bin Liu, Laxmi N. Bhuyan. 317-324 [doi]
• Using Empirical Science to Engineer Systems: Optimizing Cache for Power and PerformanceAhmed Abdallah, Wayne Wolf, Graham R. Hellestrand. 325-333 [doi]
• Reducing Leakage through Filter CacheRoberto Giorgi, Paolo Bennati. 334-341 [doi]
• Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array ArchitecturesChristophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig. 345-352 [doi]
• Hardware/Software FPGA-based Network Emulator for High-speed On-board CommunicationsSergio Saponara, Nicola E. L Insalata, Tony Bacchillone, Esa Petri, Iacopo Del Corona, Luca Fanucci. 353-359 [doi]
• Virtual Scan Chains for Online Testing of FPGA-based Embedded SystemsAlessandro Cilardo, Nicola Mazzocca, Luigi Coppolino. 360-366 [doi]
• Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA CommunicationTommaso Cecchini, Francesco Sechi, Luca Bacciarelli, Luca Mostardini, Francesco Battini, Luca Fanucci, Marco De Marinis. 367-372 [doi]
• Implementation of Self-Timed Circuits onto FPGAs Using Commercial ToolsMaurizio Tranchero, Leonardo Maria Reyneri. 373-380 [doi]
• PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital SystemsHuiju Cheng, Howard M. Heys, Cheng Wang. 383-390 [doi]
• Utilization of all Levels of Parallelism in a Processor Array with Subword ParallelismRainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich. 391-398 [doi]
• Digital Nuclear Magnetic Resonance Acquisition ChannelPaola Baldrighi, Marco Castellano, Carla Vacchi, Davide Canina, Paolo Golzi, Gianni Ferrante. 399-404 [doi]
• Fast FPGA-based Trigger and Data Acquisition System for the CERN Experiment NA62: Architecture and AlgorithmsG. Collazuol, S. Galeotti, E. Imbergamo, G. Lamanna, G. Magazzu, M. Sozzi. 405-412 [doi]
• A Novel Digital Ultrasound System for Experimental Research ActivitiesL. Bassi, E. Boni, A. Cellai, A. Dallai, F. Guidi, S. Ricci, P. Tortoli. 413-417 [doi]
• A Parallel and Modular Architecture for 802.16e LDPC CodesFrançois Charot, Christophe Wolinski, Nicolas Fau, François Hamon. 418-421 [doi]
• WirelessUSB - Performance Analysis of an Embedded System in a Peer-to-Peer ApplicationStefano Recchi, Maurizio Persichitti, Massimo Conti. 422-426 [doi]
• Design of a Distributed Embedded System for Domotic ApplicationsFrancesco Sechi, Luca Fanucci, Stefano Luschi, Simone Perini, Matteo Madesani. 427-431 [doi]
• An Embedded Acquisition System for Remote Monitoring of Tire Status in F1 Race Cars through Thermal ImagesGiovanni Danese, Mauro Giachero, Francesco Leporati, Nelson Nazzicari, M. Nobis. 432-437 [doi]
• Design of a High Performance Traffic Generator on Network ProcessorGianni Antichi, Andrea Di Pietro, Domenico Ficara, Stefano Giordano, Gregorio Procissi, Fabio Vitucci. 438-441 [doi]
• Implementation of Microprogrammed Hard Disk Drive Servo SequencerPaola Baldrighi, Marco Maurizio Maggi, Marco Castellano, Carla Vacchi, Davide Crespi, Piero Bonifacino. 442-446 [doi]
• Quantum-Dot Cellular Automata Serial ComparatorBlaz Lampreht, Luka Stepancic, Igor Vizec, Bostjan Zankar, Miha Mraz, Iztok Lebar Bajec, Primoz Pecar. 447-452 [doi]
• Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation OptimizationJosé Luis Risco-Martín, David Atienza, José Ignacio Hidalgo, Juan Lanchares. 455-463 [doi]
• Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained CircuitsPedro Garcia-Repetto, María C. Molina, Rafael Ruiz-Sautua, Guillermo Botella. 464-471 [doi]
• Multi-Objective Statistical Yield Enhancement using Evolutionary AlgorithmMinoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi. 472-479 [doi]
• Technology Library Modelling for Information-driven Circuit SynthesisLech Józwiak, Szymon Bieganski. 480-489 [doi]
• Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of MetricsMehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani. 490-493 [doi]
• A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level SynthesisGeorge Economakos, Sotirios Xydis. 494-499 [doi]
• A Novel Technique for Low Latency Data Gathering in Wireless Sensor NetworksItziar Marín, Aitzol Zuloaga, Iker Losada. 503-511 [doi]
• A Solar-powered Video Sensor Node for Energy Efficient Multimodal SurveillanceMichele Magno, Davide Brunelli, Piero Zappi, Luca Benini. 512-519 [doi]
• Exploiting WSN for Audio Surveillance Applications: The VoWSN ApproachRoberto Alesii, Fabio Graziosi, Luigi Pomante, Claudia Rinaldi. 520-524 [doi]
• Code Generation from Statecharts: Simulation of Wireless Sensor NetworksMarcello Mura, Mariagiovanna Sami. 525-532 [doi]
• Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal CheckingTsau-Shuan Wu, Alkan Cengiz, Tom W. Chen. 535-541 [doi]
• Identifying a Subset of System Verilog Assertions for Efficient Bounded Model CheckingRobert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler. 542-549 [doi]
• How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous DesignGiacomo Paci, A. Nackaerts, Francky Catthoor, Luca Benini, Paul Marchal. 550-557 [doi]
• An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay UncertaintyMorteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi. 558-565 [doi]
• SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output EvaluationA. Neslin Ismailoglu, Murat Askar. 566-571 [doi]
• VLSI Implementation of a Cryptography-Oriented Reconfigurable ArrayScott Miller, Ambrose Chu, Mihai Sima, Michael McGuire. 575-583 [doi]
• A New Array Fabric for Coarse-Grained Reconfigurable ArchitectureYoonjin Kim, Rabi N. Mahapatra. 584-591 [doi]
• Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic ReconfigurationIzhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez. 592-598 [doi]
• System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics ExperimentsMing Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch. 599-605 [doi]
• IRIS: A Firmware Design Methodology for SIMD ArchitecturesJan W. M. Jacobs, Leroy van Engelen, Jan Kuper, Gerard J. M. Smit, Rui Dai. 609-617 [doi]
• Measurement, Analysis and Modeling of RTOS System Calls TimingCarlo Brandolese, William Fornaciari. 618-625 [doi]
• Development of Functional Delay TestsEduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas. 626-632 [doi]
• Application Analysis for Parallel ProcessingMuhammad Rashid, Damien Picard, Bernard Pottier. 633-640 [doi]
• Discrete Particle Swarm Optimization for Multi-objective Design Space ExplorationGianluca Palermo, Cristina Silvano, Vittorio Zaccaria. 641-644 [doi]
• Cellflow: A Parallel Application Development Environment with Run-Time Support for the Cell BE ProcessorMartino Ruggiero, Michele Lombardi, Michela Milano, Luca Benini. 645-650 [doi]
• Exploring ISS Abstractions for Embedded Software DesignSebastien Fontaine, Luc Filion, Guy Bois. 651-655 [doi]
• High Performance Computing for Embedded System Design: A Case StudyVincenzo Catania, Gianmarco De Francisci Morales, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti. 656-659 [doi]
• Automatic Identification of Parallelism in Handel-CJoseph C. Libby, Farnaz Gharibian, Kenneth B. Kent. 660-664 [doi]
• A Variable Length Vector Pipeline Architecture Design MethodologyTakashi Kambe, Makoto Saituji. 665-668 [doi]
• Ultra-Low Power Passive UHF RFID for Wireless Sensor NetworksR. Morales-Ramos, A. Vaz, D. Pardo, Roc Berenguer. 671-675 [doi]
• Models and Tradeoffs in WSN System-Level DesignSimone Campanoni, William Fornaciari. 676-684 [doi]
• Pearson - based Analysis of Positioning Error Distribution in Wireless Sensor NetworksStefano Tennina, Marco Di Renzo, Fabio Graziosi, Fortunato Santucci. 685-692 [doi]
• On the Need for Passive Monitoring in Sensor NetworksAbdalkarim Awad, Rodrigo Nebel, Reinhard German, Falko Dressler. 693-699 [doi]
• Efficient Test Pattern Compression Method Using Hard Fault PreferringJiri Jenícek. 703-708 [doi]
• Digital Implementation of a BIST Method based on Binary ObservationsC. Le Blanc, Éric Colinet, Jérôme Juillard, Lorena Anghel. 709-713 [doi]
• Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated VerificationMohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi. 714-720 [doi]
• Power Conscious RTL Test SchedulingJaroslav Skarvada, Zdenek Kotásek, Tomas Herrman. 721-728 [doi]
• Hierarchical Analysis of Short Defects between Metal Lines in CMOS ICWitold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz. 729-734 [doi]
• Functional Verification of a USB Host ControllerPrimoz Puhar, Andrej Zemva. 735-740 [doi]
• An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford AlgebraSilvia Franchini, Antonio Gentile, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile. 743-751 [doi]
• On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic ComponentsHaridimos T. Vergos, Dimitris Bakalis. 752-759 [doi]
• A New Rounding Algorithm for Variable Latency Division and Square Root ImplementationsD. Piso, Javier D. Bruguera. 760-767 [doi]
• An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-DifferencesPedro Miguens Matutino, Leonel Sousa. 768-775 [doi]
• Logic Transformations by Multiple Wire Network AdditionEnrique San Millán, Luis Entrena, José Alberto Espejo. 779-786 [doi]
• On Projecting Sums of ProductsAnna Bernasconi, Valentina Ciriani, Roberto Cordone. 787-794 [doi]
• On Lookup Table Cascade-Based Realizations of ArbitersPetr Mikusek, Vaclav Dvorak. 795-802 [doi]
• A Fast Transformation-Based Synthesis Algorithm for Reversible CircuitsEhsan K. Ardestani, Morteza Saheb Zamani, Mehdi Sedighi. 803-806 [doi]
• A Wireless Sensor Platform for Assistive Technology ApplicationsValentina Bianchi, Ferdinando Grossi, Guido Matrella, Ilaria De Munari, Paolo Ciampolini. 809-816 [doi]
• Reliable Data Transmission over Simple Wireless Channels: A Case StudyPawel Gburzynski, Bozena Kaminska, Ashikur Rahman. 817-824 [doi]
• A Long-term Wearable Vital Signs Monitoring System using BSND. G. Guo, Francis Eng Hock Tay, L. Xu, L. M. Yu, Myo Naing Nyan, F. W. Chong, K. L. Yap, B. Xu. 825-830 [doi]
• Design of an Ultra Low-Power RFID Baseband Processor Featuring an AES Cryptography EngineAndrea Ricci, Matteo Grisanti, Ilaria De Munari, Paolo Ciampolini. 831-838 [doi]
• Transaction Level Modeling and Performance Analysis in SystemC of IEEE 802.15.4 Wireless StandardA. Mignogna, Massimo Conti, M. D Angelo, Massimo Baleani, Alberto Ferrari. 839-843 [doi]
• Architecture of a Power-Gated Wireless Sensor NodeGoran Panic, Daniel Dietterle, Zoran Stamenkovic. 844-849 [doi]
• A Hardware Implementation of CURUPIRA Block Cipher for Wireless SensorsParis Kitsos, George N. Selimis, Odysseas G. Koufopavlou, Athanassios N. Skodras. 850-853 [doi]
• Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD ToolMorteza Damavandpeyma, Siamak Mohammadi. 857-864 [doi]
• TASTE: Testability Analysis Engine and Opened Libraries for Digital Data PathJosef Strnadel. 865-872 [doi]
• Embedded Diagnostic Logic Test Exploiting RegularityHeinrich Theodor Vierhaus, René Kothe. 873-879 [doi]
• On the Complexity of Error Detection Functions for Redundant Residue Number SystemsTsutomu Sasao, Yukihiro Iguchi. 880-887 [doi]
• Programmable Numerical Function Generators for Two-Variable FunctionsShinobu Nagayama, Jon T. Butler, Tsutomu Sasao. 891-898 [doi]
• SIMD Enhancements for a Hough Transform ImplementationFrancisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata. 899-903 [doi]
• Hardware-oriented Adaptation of a Particle Swarm Optimization Algorithm for Object DetectionShahid Mehmood, Stefano Cagnoni, Monica Mordonini, Guido Matrella. 904-911 [doi]
• Acceleration of Smith-Waterman using Recursive Variable ExpansionZubair Nawaz, Zaid Al-Ars, Koen Bertels, Mudassir Shabbir. 915-922 [doi]
• Maximizing Resource Utilization by Slicing of Superscalar ArchitectureShruti Patil, Venkatesan Muthukumar. 923-930 [doi]