Simone Secchi - researchr alias

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Viewing Publication 1 - 24 from 24

2019

A Note on Sign-Changing Solutions to the NLS on the Double-Bridge GraphDiego Noja, Sergio Rolando, Simone Secchi. symmetry, 11(2):161, 2019. [doi]

2017

Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore ArchitecturesMarco Ceriani, Simone Secchi, Oreste Villa, Antonino Tumeo, Gianluca Palermo. tpds, 28(6):1635-1648, 2017. [doi]

2015

Special Issue on Architectures and Algorithms for Irregular Applications (AAIA) - Guest editors' introductionAntonino Tumeo, John Feo, Oreste Villa, Simone Secchi, Timothy G. Mattson. jpdc, 76:1-2, 2015. [doi]

2013

Prototyping hardware support for irregular applicationsMarco Ceriani, Simone Secchi, Antonino Tumeo, Oreste Villa. rapido 2012: 4 [doi]

Exploring Manycore Multinode Systems for Irregular Applications with FPGA PrototypingMarco Ceriani, Gianluca Palermo, Simone Secchi, Antonino Tumeo, Oreste Villa. fccm 2013: 238 [doi]

Exploring manycore multinode systems for irregular applications with FPGA prototypingMarco Ceriani, Simone Secchi, Antonino Tumeo, Oreste Villa, Gianluca Palermo. hotchips 2013: 1 [doi]

Exploring hardware support for scaling irregular applications on multi-node multi-core architecturesSimone Secchi, Marco Ceriani, Antonino Tumeo, Oreste Villa, Gianluca Palermo, Luigi Raffo. asap 2013: 309-313 [doi]

A runtime adaptive H.264 video-decoding MPSoC platformGiuseppe Tuveri, Simone Secchi, Paolo Meloni, Luigi Raffo, Emanuele Cannella. dasip 2013: 149-156 [doi]

2012

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable PrototyperPaolo Meloni, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, Menno Lindwer. vlsi, 2012, 2012. [doi]

Efficient Sorting on the Tilera Manycore ArchitectureAlessandro Morari, Antonino Tumeo, Oreste Villa, Simone Secchi, Mateo Valero. sbac-pad 2012: 171-178 [doi]

A Bandwidth-Optimized Multi-core Architecture for Irregular ApplicationsSimone Secchi, Antonino Tumeo, Oreste Villa. ccgrid 2012: 580-587 [doi]

Designing Next-Generation Massively Multithreaded Architectures for Irregular ApplicationsAntonino Tumeo, Simone Secchi, Oreste Villa. Computer, 45(8):53-61, 2012. [doi]

Fast and Accurate Simulation of the Cray XMT Multithreaded SupercomputerOreste Villa, Antonino Tumeo, Simone Secchi, Joseph B. Manzano. tpds, 23(12):2266-2279, 2012. [doi]

2011

2010

2008

A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip DesignsFrancesca Palumbo, Simone Secchi, Danilo Pani, Luigi Raffo. samos 2008: 96-105 [doi]

A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode SwitchingSimone Secchi, Francesca Palumbo, Danilo Pani, Luigi Raffo. dsd 2008: 141-148 [doi]

2007

A Surface Tension and Coalescence Model for Dynamic Distributed Resources Allocation in Massively Parallel Processors on-ChipFrancesca Palumbo, Danilo Pani, Luigi Raffo, Simone Secchi. In Natalio Krasnogor, Giuseppe Nicosia, Mario Pavone, David A. Pelta, editors, Nature Inspired Cooperative Strategies for Optimization (NICSO 2007). Volume 129 of Studies in Computational Intelligence, pages 335-345, Springer, 2007. [doi]

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