Table of Contents

• Reconfigurable computing in the era of post-silicon scaling [panel discussion]Eric Chung, Doug Burger, Mike Butts, Jan Gray, Chuck Thacker, Kees A. Vissers, John Wawrzynek. [doi]
• Parallel Computation of Skyline QueriesLouis Woods, Gustavo Alonso, Jens Teubner. 1-8 [doi]
• Minerva: Accelerating Data Analysis in Next-Generation SSDsArup De, Maya Gokhale, Rajesh Gupta, Steven Swanson. 9-16 [doi]
• Accelerating Join Operation for Relational Databases with FPGAsRobert Halstead, Bharat Sukhwani, Hong Min, Mathew Thoennes, Parijat Dube, Sameh W. Asaad, Balakrishna Iyer. 17-20 [doi]
• Boosting Memory Performance of Many-Core FPGA Device through Dynamic Precedence GraphYu Bai, Abigail Fuentes, Michael Riera, Mohammed Alawad, Mingjie Lin. 21-24 [doi]
• Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial ReconfigurationChristopher Dennl, Daniel Ziener, Jürgen Teich. 25-28 [doi]
• Accuracy-Performance Tradeoffs on an FPGA through OverclockingKan Shi, David Boland, George A. Constantinides. 29-36 [doi]
• Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using RazorAlexander Brant, Ameer Abdelhadi, Douglas H. H. Sim, Shao Lin Tang, Michael Xi Yue, Guy G. F. Lemieux. 37-44 [doi]
• Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx DevicesEddie Hung, Fatemeh Eslami, Steven J. E. Wilton. 45-52 [doi]
• A Case for Heterogeneous Technology-Mapping: Soft Versus Hard MultiplexersMadhura Purnaprajna, Paolo Ienne. 53-56 [doi]
• Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped CircuitsAbdulazim Amouri, Hussam Amrouch, Thomas Ebi, Jörg Henkel, Mehdi Baradaran Tahoori. 57-60 [doi]
• On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAsAurelio Morales-Villanueva, Ann Gordon-Ross. 61-64 [doi]
• A High Throughput No-Stall Golomb-Rice Hardware DecoderRoger Moussalli, Walid A. Najjar, Xi Luo, Amna Khan. 65-72 [doi]
• Image Segmentation Using Hardware Forest ClassifiersRichard Neil Pittman, Alessandro Forin, Antonio Criminisi, Jamie Shotton, Atabak Mahram. 73-80 [doi]
• A Reconfigurable Architecture for 1-D and 2-D Discrete Wavelet TransformQing Sun, Jiang Jiang, Yongxin Zhu, Yuzhuo Fu. 81-84 [doi]
• High Speed Video Processing Using Fine-Grained Processing on FPGA PlatformZhi Ping Ang, Akash Kumar, Yajun Ha. 85-88 [doi]
• The Effect of Compiler Optimizations on High-Level Synthesis for FPGAsQijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Dean Brown, Jason Helge Anderson. 89-96 [doi]
• Automating Elimination of Idle Functions by Run-Time ReconfigurationXinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu. 97-104 [doi]
• Open-Source Bitstream GenerationRitesh Kumar Soni, Neil Steiner, Matthew French. 105-112 [doi]
• ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory InterconnectsEric S. Chung, Michael Papamichael. 113-116 [doi]
• PRML: A Modeling Language for Rapid Design Exploration of Partially Reconfigurable FPGAsRohit Kumar, Ann Gordon-Ross. 117-120 [doi]
• Atacama: An Open FPGA-Based Platform for Mixed-Criticality Communication in Multi-segmented Ethernet NetworksGonzalo Carvajal, Miguel Figueroa, Robert Trausmuth, Sebastian Fischmeister. 121-128 [doi]
• Latency-Optimized Networks for Clustering FPGAsTrevor Bunker, Steven Swanson. 129-136 [doi]
• A Range and Scaling Study of an FPGA-Based Digital Wireless Channel EmulatorScott Buscemi, William V. Kritikos, Ron Sass. 137-144 [doi]
• Enabling Hardware Exploration in Software-Defined Networking: A Flexible, Portable OpenFlow SwitchAsif Khan, Nirav Dave. 145-148 [doi]
• An FPGA Based PCI-E Root Complex Architecture for Standalone SOPCsYingjie Cao, Yongxin Zhu, Xu Wang, Jiang Jiang, Meikang Qiu. 149-152 [doi]
• Application Composition and Communication Optimization in Iterative Solvers Using FPGAsAbid Rafique, Nachiket Kapre, George A. Constantinides. 153-160 [doi]
• Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard TransformDavid B. Thomas. 161-168 [doi]
• Hardware-Software Codesign for Embedded Numerical AccelerationRanko Sredojevic, Andrew Wright, Vladimir Stojanovic. 169-172 [doi]
• FAssem: FPGA Based Acceleration of De Novo Genome AssemblyB. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier. 173-176 [doi]
• Accelerating the Computation of Induced Dipoles for Molecular Mechanics with Dataflow EnginesFrederico Pratas, Diego Oriato, Oliver Pell, Ricardo A. Mata, Leonel Sousa. 177-180 [doi]
• On Optimizing the Arithmetic Precision of MCMC AlgorithmsGrigorios Mingas, Farhan Rahman, Christos-Savvas Bouganis. 181-188 [doi]
• Exploiting Input Parameter Uncertainty for Reducing Datapath Precision of SPICE Device ModelsNachiket Kapre. 189-197 [doi]
• Efficient Large Integer Squarers on FPGASimin Xu, Suhaib A. Fahmy, Ian Vince McLoughlin. 198-201 [doi]
• Elementary Function Implementation with Optimized Sub Range Polynomial EvaluationMartin Langhammer, Bogdan Pasca. 202-205 [doi]
• High-Level Description and Synthesis of Floating-Point Accumulators on FPGAMarc-André Daigneault, Jean-Pierre David. 206-209 [doi]
• Reconfigurable Acceleration of Short Read MappingJames Arram, Kuen Hung Tsoi, Wayne Luk, Peiyong Jiang. 210-217 [doi]
• An FPGA-Based Data Flow Engine for Gaussian Copula ModelHuabin Ruan, Xiaomeng Huang, Haohuan Fu, Guangwen Yang, Wayne Luk, Sébastien Racanière, Oliver Pell, Wenjing Han. 218-225 [doi]
• A Delay-based PUF Design Using Multiplexers on FPGAMiaoqing Huang, Shiming Li. 226 [doi]
• Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential CircuitsJiliang Zhang, Yaping Lin, Yongqiang Lu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian. 227 [doi]
• A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA FrequencyCheng Liu, Colin Yu Lin, Hayden Kwok-Hay So. 228 [doi]
• FPGA Simulation Engine for Customized Construction of Neural MicrocircuitJason Cong, Hugh T. Blair, Di Wu. 229 [doi]
• Global Atmospheric Simulation on a Reconfigurable PlatformLin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Guangwen Yang. 230 [doi]
• An Approach to a Fully Automated Partial Reconfiguration Design FlowKizheppatt Vipin, Suhaib A. Fahmy. 231 [doi]
• A Multithreaded VLIW Soft Processor FamilyKalin Ovtcharov, Ilian Tili, J. Gregory Steffan. 232 [doi]
• A Configurable Architecture for a Visual Saliency System and Its Application in RetailNandhini Chandramoorthy, Siddharth Advani, Kevin M. Irick, Vijaykrishnan Narayanan. 233 [doi]
• The Impact of Hardware Communication on a Heterogeneous Computing SystemShanyuan Gao, Bin Huang, Ron Sass. 234 [doi]
• An Evaluation of High-Performance Embedded Processing on MPPAsZain-ul-Abdin, Bertil Svensson. 235 [doi]
• A Fast and Accurate FPGA-Based Fault Injection SystemThomas Schweizer, Dustin Peterson, Johannes M. Kuhn, Tommy Kuhn, Wolfgang Rosenstiel. 236 [doi]
• Memory Access Scheduling on the Convey HC-1Zheming Jin, Jason D. Bakos. 237 [doi]
• Exploring Manycore Multinode Systems for Irregular Applications with FPGA PrototypingMarco Ceriani, Gianluca Palermo, Simone Secchi, Antonino Tumeo, Oreste Villa. 238 [doi]
• Global Control and Storage Synthesis for a System Level Synthesis ApproachShuo Li, Nasim Farahini, Ahmed Hemani. 239 [doi]