Abstract is missing.
- A Code-Based Analytical Approach for Using Separate Device Coprocessors in Computing SystemsVolker Hampel, Grigori Goronzy, Erik Maehle. 1-12 [doi]
- Scalability Evaluation of a Polymorphic Register File: A CG Case StudyCatalin Bogdan Ciobanu, Xavier Martorell, Georgi Kuzmanov, Alex Ramírez, Georgi Gaydadjiev. 13-25 [doi]
- Experiences with String Matching on the Fermi ArchitectureAntonino Tumeo, Simone Secchi, Oreste Villa. 26-37 [doi]
- Using Amdahl s Law for Performance Analysis of Many-Core SoC Architectures Based on Functionally Asymmetric ProcessorsHao Shen, Frédéric Pétrot. 38-49 [doi]
- Application-Aware Power Saving for Online Transaction Processing Using Dynamic Voltage and Frequency Scaling in a Multicore EnvironmentYuto Hayamizu, Kazuo Goda, Miyuki Nakano, Masaru Kitsuregawa. 50-61 [doi]
- Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image RegistrationRichard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert. 62-73 [doi]
- Emulating Transactional Memory on FPGA MultiprocessorsMatteo Pusceddu, Simone Ceccolini, Antonino Tumeo, Gianluca Palermo, Donatella Sciuto. 74-85 [doi]
- Architecture of an Adaptive Test System Built on FPGAsJörg Sachße, Heinz-Dietrich Wuttke, Steffen Ostendorff, Jorge H. Meza Escobar. 86-97 [doi]
- An Extensible Framework for Context-Aware Smart EnvironmentsAngham A. Sabagh, Adil Al-Yasiri. 98-109 [doi]
- Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3Jaroslav Sykora, Leos Kafka, Martin Danek, Lukas Kohout. 110-121 [doi]
- A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by HardwareStefan Metzlaff, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer. 122-134 [doi]
- Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling StrategyMarius Grannæs, Magnus Jahre, Lasse Natvig. 135-146 [doi]
- Compiler-Assisted Selection of a Software Transactional Memory SystemMartin Schindewolf, Alexander Esselson, Wolfgang Karl. 147-157 [doi]
- An Instruction to Accelerate Software CachesArnaldo Azevedo, Ben H. H. Juurlink. 158-170 [doi]
- Memory-, Bandwidth-, and Power-Aware Multi-core for a Graph Database WorkloadPedro Trancoso, Norbert Martínez-Bazan, Josep-Lluis Larriba-Pey. 171-182 [doi]
- A Light-Weight Approach for Online State Classification of Self-organizing Parallel SystemsDavid Kramer, Rainer Buchty, Wolfgang Karl. 183-194 [doi]
- Towards Organic Active Vision Systems for Visual SurveillanceMichael Wittke, Carsten Grenz, Jörg Hähner. 195-206 [doi]
- Emergent Behaviour in Collaborative Indoor Localisation: An Example of Self-organisation in Ubiquitous Sensing SystemsKamil Kloch, Gerald Pirkl, Paul Lukowicz, Carl Fischer. 207-218 [doi]
- An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel AllocationSon Truong Nguyen, Shigeru Oyanagi. 219-230 [doi]
- Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut PathsNasibeh Teimouri, Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad. 231-242 [doi]
- A Learning-Based Approach to the Automated Design of MPSoC NetworksOscar Almer, Nigel P. Topham, Björn Franke. 243-258 [doi]
- Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice VersaAndreas Kern, Dominik Reinhard, Thilo Streichert, Jürgen Teich. 259-270 [doi]