Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper - researchr publication

researchr

You are not signed in
Sign in
Sign up

Paolo Meloni, Simone Secchi, Luigi Raffo. Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper. In 18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010. pages 43-48, IEEE, 2010. [doi]

Abstract is missing.

runs on WebDSL