Paolo Meloni, Simone Secchi, Luigi Raffo. Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper. In 18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010. pages 43-48, IEEE, 2010. [doi]
@inproceedings{MeloniSR10,
title = {Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper},
author = {Paolo Meloni and Simone Secchi and Luigi Raffo},
year = {2010},
doi = {10.1109/VLSISOC.2010.5642625},
url = {http://dx.doi.org/10.1109/VLSISOC.2010.5642625},
tags = {rule-based},
researchr = {https://researchr.org/publication/MeloniSR10},
cites = {0},
citedby = {0},
pages = {43-48},
booktitle = {18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010},
publisher = {IEEE},
}