Abstract is missing.
- A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoCHajer Chtioui, Rabie Ben Atitallah, Smaïl Niar, Jean-Luc Dekeyser, Mohamed Abid. 3-10 [doi]
- An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCsShadi Traboulsi, Michael Meitinger, Rainer Ohlendorf, Andreas Herkersdorf. 11-18 [doi]
- An Effective Replacement Strategy of Cache Memory for an SMT ProcessorYoshiyasu Ogasawara, Hironori Nakajo. 19-25 [doi]
- An Evaluation of Behaviors of S-NUCA CMPs Running Scientific WorkloadPierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, Marco Solinas. 26-33 [doi]
- A Priority-Based Budget Scheduler with Conservative Dataflow ModelMarcel Steine, Marco Bekooij, Maarten Wiggers. 37-44 [doi]
- Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient GenerationAlexandru Amaricai, Oana Boncalo. 45-49 [doi]
- Distributed Collaborative Design of a Mixed-Signal IP ComponentAdam Pawlak, Piotr Penkala, Pawel Fras, Wojciech Sakowski, Gunter Grau, Szymon Grzybek, Alexander Stanitzki. 50-57 [doi]
- A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM SignalingMohammad Fattah, Soodeh Aghli Moghaddam, Siamak Mohammadi. 61-66 [doi]
- Improving Latency of Quantum Circuits by Gate ExchangingNaser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi. 67-73 [doi]
- Run-Time Reconfigurable Array Using Magnetic RAMVictor Silva, LuÃs Bica Oliveira, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto. 74-81 [doi]
- Robustness Check for Multiple Faults Using Formal TechniquesStefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler. 85-90 [doi]
- Instruction Precomputation for Fault DetectionDemid Borodin, Ben H. H. Juurlink, Stefanos Kaxiras. 91-99 [doi]
- Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State LogicWerner Friesenbichler, Andreas Steininger. 100-107 [doi]
- High Availability Fault Tolerant Architectures Implemented into FPGAsMartin Straka, Zdenek Kotásek. 108-115 [doi]
- Data Encoding for Low-Power in Wormhole-Switched Networks-on-ChipMaurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania. 119-126 [doi]
- Exploration of Slot Allocation for On-Chip TDM Virtual CircuitsLi Tong, Zhonghai Lu, Hua Zhang. 127-132 [doi]
- Mapping Algorithms for NoC-Based Heterogeneous MPSoC PlatformsAmit Kumar Singh, Wu Jigang, Alok Prakash, Thambipillai Srikanthan. 133-140 [doi]
- Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip NetworksAlexander Wei Yin, Liang Guang, Ethiopia Nigussie, Pasi Liljeberg, Jouni Isoaho, Hannu Tenhunen. 141-146 [doi]
- Power Management Aware Low Leakage Behavioural SynthesisSven Rosinger, Kiril Schroder, Wolfgang Nebel. 149-156 [doi]
- Variation-tolerant Design Using Residue Number SystemIoannis Kouretas, Vassilis Paliouras. 157-163 [doi]
- Optimized Reconfigurable RTL Components for Performance Improvements During High-Level SynthesisGeorge Economakos, Sotirios Xydis. 164-171 [doi]
- Combined SD-RNS Constant MultiplicationE. Vassalos, Dimitris Bakalis. 172-179 [doi]
- Temperature- and Cost-Aware Design of 3D Multiprocessor ArchitecturesAyse Kivilcim Coskun, Andrew B. Kahng, Tajana Simunic Rosing. 183-190 [doi]
- Calibration Method for a CMOS 0.06mm:::2::: 150MS/s 8-bit ADCNikos Petrellis, Michael K. Birbas, John C. Kikidis, Alexios N. Birbas. 191-195 [doi]
- Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy ApplicationsJose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi, Javier Sosa, Héctor Navarro. 196-199 [doi]
- An Adaptive Unicast/Multicast Routing Algorithm for MPSoCsMasoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen. 203-206 [doi]
- Model-Driven Design of Embedded Multimedia Applications on SoCsAdolf Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser. 207-210 [doi]
- GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform GridsAlexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França. 211-216 [doi]
- Using Integer Linear Programming in Test-bench Generation for Evaluating Communication ProcessorsEric Senn, David Monnereau, André Rossi, Nathalie Julien. 217-220 [doi]
- Reliability Estimation ProcessTobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus. 221-224 [doi]
- Time-Varying Network Fault Model for the Design of Dependable Networked Embedded SystemsFranco Fummi, Davide Quaglia, Francesco Stefanni. 225-228 [doi]
- Block-Level Fault Model-Free Debug and Diagnosis in Digital SystemsRaimund Ubar, Sergei Kostin, Jaan Raik. 229-232 [doi]
- High Performance Image Processing on a Massively Parallel Processor ArrayRoberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera. 233-236 [doi]
- Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test EnvironmentZhiyuan He, Zebo Peng, Petru Eles. 239-246 [doi]
- Low Power Encoding in NoCs Based on Coupling Transition AvoidanceMeysam Taassori, Shaahin Hessabi. 247-254 [doi]
- Hierarchical NoCs for Optimized Access to Shared Memory and IO ResourcesAndreas Lankes, Thomas Wild, Andreas Herkersdorf. 255-262 [doi]
- Storage Architecture for an On-chip Multi-core ProcessorMengxiao Liu, Weixing Ji, Jiaxin Li, Xing Pu. 263-270 [doi]
- Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAsRui Duarte, Horácio C. Neto, Mário P. Véstias. 273-280 [doi]
- A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EACFeng Liu, Fariborz Fereydouni-Forouzandeh, Otmane Aït Mohamed, Gang Chen, Xiaoyu Song, Qingping Tan. 281-286 [doi]
- Streaming Reduction CircuitMarco Gerards, Jan Kuper, André B. J. Kokkeler, Bert Molenkamp. 287-292 [doi]
- Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder EstimationDaniel Piso Fernandez, Javier D. Bruguera. 293-300 [doi]
- Pulse Generation for On-chip Data TransmissionSimon Hollis. 303-310 [doi]
- High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V OutputJose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi. 311-314 [doi]
- Performance-Effective Compaction of Standard-Cell Libraries for Digital DesignAndrea Ricci, Ilaria De Munari, Paolo Ciampolini. 315-322 [doi]
- On the Risk of Fault Coupling over the Chip SubstratePeter Tummeltshammer, Andreas Steininger. 325-332 [doi]
- Heterogeneous Multiprocessor Synthesis under Performance and Reliability ConstraintsMakoto Sugihara. 333-340 [doi]
- A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded SystemsJimmy Tarrillo, Leticia Maria Bolzani Pohls, Fabian Vargas. 341-347 [doi]
- Reliable Railway Station System Based on Regular Structure Implemented in FPGAJaroslav Borecky, Pavel KubalÃk, Hana Kubatova. 348-354 [doi]
- Dependable Controller Design Using Polymorphic CountersRichard Ruzicka. 355-362 [doi]
- Internet-Router Buffered Crossbars Based on Networks on ChipKees Goossens, Lotfi Mhamdi, Iria Varela Senin. 365-374 [doi]
- Network-on-Chip Architecture Exploration FrameworkTimo Schönwald, Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel. 375-382 [doi]
- Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-ChipGiovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. 383-389 [doi]
- Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case StudyAlexandre Guerre, Nicolas Ventroux, Raphael David, Alain Mérigot. 390-397 [doi]
- A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC TuningAhmed Mohamed AbdelHamid, Ankur Anchlia, Stylianos Mamagkakis, Miguel Corbalan Miranda, Bart Dierickx, Maarten Kuijk. 401-408 [doi]
- Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple ProcessorsAnca Mariana Molnos, Kees Goossens. 409-418 [doi]
- Compilation Technique for Loop Overhead MinimizationNikolas Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Dimitrios Soudris. 419-426 [doi]
- Pipelining-Based High Throughput Low Energy Mapping on Network-on-ChipMing-Yan Yu, Ming Li, Jun-Jie Song, Fang-Fa Fu, Yu-Xin Bai. 427-432 [doi]
- Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio TechniquesDominique Nussbaum, Karim Khalfallah, Christophe Moy, Amor Nafkha, Pierre Leray, Julien Delorme, Jacques Palicot, Jerome Martin, Fabien Clermidy, Bertrand Mercier, Renaud Pacalet. 435-440 [doi]
- Architecture and DSP Implementation of a DVB-S2 Baseband DemodulatorPanayiotis Savvopoulos, Nikolaos Papandreou, Theodore Antonakopoulos. 441-448 [doi]
- An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and ApplicationFabien Clermidy, Romain Lemaire, Xavier Popon, Dimitri Ktenas, Yvain Thonnart. 449-456 [doi]
- Deductive Fault Simulation for Asynchronous Sequential CircuitsRoland Dobai, Elena Gramatová. 459-464 [doi]
- ARROW - A Generic Hardware Fault Injection Tool for NoCsMichael Birner, Thomas Handl. 465-472 [doi]
- A Fault Tolerant NoC Architecture for Reliability Improvement and Latency ReductionAmir Ehsani Zonouz, Mehrdad Seyrafi, Arghavan Asad, Mohsen Soryani, Mahmood Fathy, Reza Berangi. 473-480 [doi]
- Reliability Analysis of Qubit Data Movement for Distributed Quantum ComputationOana Boncalo, Alexandru Amaricai. 481-487 [doi]
- High Reliable Remote Terminal Unit for Space ApplicationsDavid Guzman, Manuel Prieto, Daniel Garcia, Victor Ruiz, Javier Almena, Sebastian Sanchez, Daniel Meziat. 488-493 [doi]
- SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet TransformAsadollah Shahbahrami, Ben H. H. Juurlink. 497-504 [doi]
- Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch MechanismZheng Shen, Hu He, Yihe Sun. 505-512 [doi]
- Iterative Algorithm for Compound Instruction Selection with Register CoalescingMinwook Ahn, Jonghee M. Youn, Youngkyu Choi, Doosan Cho, Yunheung Paek. 513-520 [doi]
- CPLD-oriented Synthesis of Finite State MachinesRobert Czerwinski, Dariusz Kania. 521-528 [doi]
- Architecture-Driven Synthesis of Reconfigurable CellsChristophe Wolinski, Krzysztof Kuchcinski, Erwan Raffin, François Charot. 531-538 [doi]
- An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid CommunicationJochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick. 539-546 [doi]
- Composable Resource Sharing Based on Latency-Rate ServersBenny Akesson, Andreas Hansson, Kees Goossens. 547-555 [doi]
- A MPSoC Prototyping Platform for Flexible Radio ApplicationsDamien Hedde, Pierre-Henri Horrein, Frédéric Pétrot, Robin Rolland, Franck Rousseau. 559-566 [doi]
- Abstract Description of System Application and Hardware Architecture for Hardware/Software Code GenerationAmin El Mrabti, Hamed Sheibanyrad, Frédéric Rousseau, Frédéric Pétrot, Romain Lemaire, Jérôme Martin. 567-574 [doi]
- Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication SystemsMaroun Ojail, Raphaël David, Stéphane Chevobbe, Didier Demigny. 575-581 [doi]
- Flexible Architectures for LDPC Decoders Based on Network on Chip ParadigmFabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, Michel Jézéquel. 582-589 [doi]
- High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor LogicJose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi. 593-596 [doi]
- Power Aware Fulfilment of Latency Requirements by Exploiting Heterogeneity in Wireless Sensor and Actuator NetworksJoris Borms, Kris Steenhaut, Bart Lemmens, Ann Nowé. 597-600 [doi]
- The Case for a Balanced Decomposition ProcessJan Schmidt, Petr Fiser. 601-604 [doi]
- Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost MinimizationPetr Mikusek, Václav Dvorák. 605-608 [doi]
- Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 DecoderThomas Tsiolakis, Nikos Konofaos, George Alexiou. 609-612 [doi]
- Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor ArchitectureMarius Gligor, Nicolas Fournel, Frédéric Pétrot. 613-616 [doi]
- Survey of Test Data Compression Technique Emphasizing Code Based SchemesUsha Sandeep Mehta, K. S. Dasgupta, N. M. Devashrayee. 617-620 [doi]
- A Concept for Logic Self RepairTobias Koal, Heinrich Theodor Vierhaus, Daniel Scheit. 621-624 [doi]
- A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous ProcessorLuis A. Tarazona, Doug A. Edwards, Luis A. Plana. 627-634 [doi]
- An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of InstructionsSalvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López, José Duato. 635-642 [doi]
- An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded ArchitecturesVincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Gianmarco De Francisci Morales. 643-650 [doi]
- Energy and Performance Model of a SPARC Leon3 ProcessorSandro Penolazzi, Luca Bolognino, Ahmed Hemani. 651-656 [doi]
- Acceleration of MELP Algorithm Using DSP Coprocessor with Extended RegistersLu Gao, Li Guo, Canxing Lu. 659-666 [doi]
- FPGA Accelerator for RNA Secondary Structure PredictionArturo Diaz-Perez, Mario Alberto Garcia Martinez. 667-671 [doi]
- An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation AlgorithmGiovanni Danese, Mauro Giachero, Francesco Leporati, G. Matrone, Nelson Nazzicari. 672-679 [doi]
- xMAML: A Modeling Language for Dynamically Reconfigurable ArchitecturesJulien Lallet, Sébastien Pillement, Olivier Sentieys. 680-687 [doi]
- A High Performance Hardware Architecture for One Bit Transform Based Motion EstimationAbdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu. 691-698 [doi]
- Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA EvolutionRizwan Asghar, Di Wu, Johan Eilert, Dake Liu. 699-706 [doi]
- GPU Accelerated Solver of Time-Dependent Air Pollutant Transport EquationsVaclav Simek, Radim Dvorak, Frantisek Zboril, VladimÃr Drábek. 707-713 [doi]
- A Reconfigurable Frame Interpolation Hardware Architecture for High Definition VideoOzgur Tasdizen, Ilker Hamzaoglu. 714-719 [doi]
- Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM ModelsAntonio da Silva, Sebastian Sanchez. 723-728 [doi]
- Design of a Highly Dependable Beamforming ChipXiao Zhang, Hans G. Kerkhoff. 729-735 [doi]
- One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean AlgorithmApostolos P. Fournaris, Odysseas G. Koufopavlou. 736-741 [doi]
- Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial LinksRaj Kumar Nagpal, Rakesh Malik, Jai Narayan Tripathi. 742-745 [doi]
- Synthesizing Reversible Circuits for Irreversible FunctionsD. Michael Miller, Robert Wille, Gerhard W. Dueck. 749-756 [doi]
- A Fast SOP Minimizer for Logic Funcions Described by Many Product TermsPetr Fiser, David Toman. 757-764 [doi]
- Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound VariablesTsutomu Sasao, Takaaki Nakamura, Munehiro Matsuura. 765-772 [doi]
- Logic Minimization and Testability of 2SPP-P-CircuitsAnna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa. 773-780 [doi]
- FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral HashBrian Baldwin, Andrew Byrne, Mark Hamilton, Neil Hanley, Robert P. McEvoy, Weibo Pan, William P. Marnane. 783-790 [doi]
- Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL MethodologyGeorge Kiokes, George Economakos, Angelos Amditis, Nikolaos K. Uzunoglu. 791-798 [doi]
- Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource OptimizationMario Alberto Ibarra-Manzano, Dora Luz Almanza-Ojeda, Michel Devy, Jean-Louis Boizard, Jean-Yves Fourniols. 799-805 [doi]
- The Parallel Sieve Method for a Virus Scanning EngineHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura. 809-816 [doi]
- Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse AlgorithmHamid Reza Ahmadi, Ali Afzali-Kusha. 817-822 [doi]
- Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect HashingJan Kastil, Jan Korenek, Ondrej Lengál. 823-829 [doi]
- An FPGA-Based Embedded System for a Sailing RobotJosé Carlos Alves, Nuno Alexandre Cruz. 830-837 [doi]
- Ad-hoc WSN in Biological ResearchPerfecto Mariño Espiñeira, Fernando Pérez-Fontán, Miguel Angel DomÃnguez, Santiago Otero. 841-848 [doi]
- Low Power Free Space Optical Communication in Wireless Sensor NetworksJames Mathews, Matthew Barnes, D. K. Arvind. 849-856 [doi]
- A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs NodesCarlo Brandolese, William Fornaciari. 857-864 [doi]
- Remote Monitoring of Thermal Performance of Salinity Gradient Solar PondsMilan Nenad Simic, Randeep Singh, Louis Doukas, Aliakbar Akbarzadeh. 865-869 [doi]