Abstract is missing.
- Has anything changed in electronic design since 1983?Mike Muller. 1 [doi]
- Embedded systems design - Scientific challenges and work directionsJoseph Sifakis. 2 [doi]
- A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chipHuaxi Gu, Jiang Xu, Wei Zhang. 3-8 [doi]
- SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chipsCiprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli. 9-14 [doi]
- User-centric design space exploration for heterogeneous Network-on-Chip platformsChen-Ling Chou, Radu Marculescu. 15-20 [doi]
- A highly resilient routing algorithm for fault-tolerant NoCsDavid Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David Blaauw. 21-26 [doi]
- Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architectureSean Whitty, Henning Sahlbach, Rolf Ernst, Wolfram Putzke-Röming. 27-32 [doi]
- An ILP formulation for task mapping and scheduling on multi-core architecturesYing Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tughrul Arslan. 33-38 [doi]
- DPR in high energy physicsWenxue Gao, Andreas Kugel, Reinhard Männer, Norbert Abel, Nick Meier, Udo Kebschull. 39-44 [doi]
- A flexible layered architecture for accurate digital baseband algorithm development and verificationAmirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn. 45-50 [doi]
- Lifetime reliability-aware task allocation and scheduling for MPSoC platformsLin Huang, Feng Yuan, Qiang Xu. 51-56 [doi]
- Integrated scheduling and synthesis of control applications on distributed embedded systemsSoheil Samii, Anton Cervin, Petru Eles, Zebo Peng. 57-62 [doi]
- Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitudeChengmo Yang, Alex Orailoglu. 63-68 [doi]
- Pipelined data parallel task mapping/scheduling technique for MPSoCHoeseok Yang, Soonhoi Ha. 69-74 [doi]
- Joint logic restructuring and pin reordering against NBTI-induced performance degradationKai-Chiang Wu, Diana Marculescu. 75-80 [doi]
- A self-adaptive system architecture to address transistor agingOmer Khan, Sandip Kundu. 81-86 [doi]
- Masking timing errors on speed-paths in logic circuitsMihir R. Choudhury, Kartik Mohanram. 87-92 [doi]
- WCRT algebra and interfaces for esterel-style synchronous processingMichael Mendler, Reinhard von Hanxleden, Claus Traulsen. 93-98 [doi]
- Reliable mode changes in real-time systems with fixed priority or EDF schedulingNikolay Stoimenov, Simon Perathoner, Lothar Thiele. 99-104 [doi]
- Improved worst-case response-time calculations by upper-bound conditionsVictor Pollex, Steffen Kollmann, Karsten Albers, Frank Slomka. 105-110 [doi]
- A generalized scheduling approach for dynamic dataflow applicationsWilliam Plishker, Nimish Sane, Shuvra S. Bhattacharyya. 111-116 [doi]
- Optimizing data flow graphs to minimize hardware implementationDaniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon. 117-122 [doi]
- Multi-clock Soc design using protocol conversionRoopak Sinha, Partha S. Roop, Samik Basu, Zoran Salcic. 123-128 [doi]
- A formal approach to design space exploration of protocol convertersKarin Avnit, Arcot Sowmya. 129-134 [doi]
- Model-based synthesis and optimization of static multi-rate image processing algorithmsJoachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich. 135-140 [doi]
- Panel session - Consolidation, a modern "Moor of Venice" taleMarco Casale-Rossi, Giovanni De Micheli. 141 [doi]
- Variation resilient adaptive controller for subthreshold circuitsBiswajit Mishra, Bashir M. Al-Hashimi, Mark Zwolinski. 142-147 [doi]
- Minimization of NBTI performance degradation using internal node controlDavid R. Bild, Gregory E. Bok, Robert P. Dick. 148-153 [doi]
- Physically clustered forward body biasing for variability compensation in nanometer CMOS designAshoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii. 154-159 [doi]
- An event-guided approach to reducing voltage noise in processorsMeeta Sharma Gupta, Vijay Janapa Reddi, Glenn H. Holloway, Gu-Yeon Wei, David M. Brooks. 160-165 [doi]
- Design and implementation of a database filter for BLAST accelerationPanagiotis Afratis, Constantinos Galanakis, Euripides Sotiriades, Georgios-Grigorios Mplemenos, Grigorios Chrysos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos. 166-171 [doi]
- A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAsKostas Siozios, Vasilis F. Pavlidis, Dimitrios Soudris. 172-177 [doi]
- Priority-based packet communication on a bus-shaped structure for FPGA-systemsOliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser. 178-183 [doi]
- Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processorSyed Zahid Ahmed, Julien Eydoux, Laurent Rouge, Jean-Baptiste Cuelle, Gilles Sassatelli, Lionel Torres. 184-189 [doi]
- Functional qualification of TLM verificationNicola Bombieri, Franco Fummi, Graziano Pravadelli, Mark Hampton, Florian Letombe. 190-195 [doi]
- Solver technology for system-level to RTL equivalence checkingAlfred Kölbl, Reily Jacoby, Himanshu Jain, Carl Pixley. 196-201 [doi]
- A high-level debug environment for communication-centric debugKees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad. 202-207 [doi]
- Cache aware compression for processor debug supportAnant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan. 208-213 [doi]
- Fault insertion testing of a novel CPLD-based fail-safe systemGerhard Grießnig, Roland Mader, Christian Steger, Reinhold Weiss. 214-219 [doi]
- Test architecture design and optimization for three-dimensional SoCsLi Jiang, Lin Huang, Qiang Xu. 220-225 [doi]
- A co-design approach for embedded system modeling and code generation with UML and MARTEJorgiano Vidal, Florent de Lamotte, Guy Gogniat, Philippe Soulard, Jean-Philippe Diguet. 226-231 [doi]
- Componentizing hardware/software interface designKecheng Hao, Fei Xie. 232-237 [doi]
- A UML frontend for IP-XACT-based IP managementTim Schattkowsky, Tao Xie, Wolfgang Mueller. 238-243 [doi]
- Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGATero Arpinen, Tapio Koskinen, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen. 244-249 [doi]
- Aelite: A flit-synchronous Network on Chip with composable and predictable servicesAndreas Hansson, Mahesh Subburaman, Kees Goossens. 250-255 [doi]
- Configurable links for runtime adaptive on-chip communicationMohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel. 256-261 [doi]
- Synthesis of low-overhead configurable source routing tables for network interfacesIgor Loi, Federico Angiolini, Luca Benini. 262-267 [doi]
- SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systemsAbelardo Jara-Berrocal, Ann Gordon-Ross. 268-273 [doi]
- Analog layout synthesis - Recent advances in topological approachesHelmut Gräb, Florin Balasa, R. Castro-López, Yu-wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, Martin Strasser. 274-279 [doi]
- An accurate interconnect thermal model using equivalent transmission line circuitBaohua Wang, Pinaki Mazumder. 280-283 [doi]
- Analogue mixed signal simulation using spice and SystemCTobias Kirchner, Nico Bannow, Christoph Grimm. 284-287 [doi]
- Reliability aware through silicon via planning for 3D stacked ICsAmirali Shayan Arani, Xiang Hu, He Peng, Chung-Kuan Cheng, Wenjian Yu, Mikhail Popovich, Thomas Toms, Xiaoming Chen. 288-291 [doi]
- A study on placement of post silicon clock tuning buffers for mitigating impact of process variationKelageri Nagaraj, Sandip Kundu. 292-295 [doi]
- Analysis and optimization of NBTI induced clock skew in gated clock treesAshutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan. 296-299 [doi]
- Bitstream relocation with local clock domains for partially reconfigurable FPGAsAdam Flynn, Ann Gordon-Ross, Alan D. George. 300-303 [doi]
- Parallel transistor level full-chip circuit simulationHe Peng, Chung-Kuan Cheng. 304-307 [doi]
- Performance-driven dual-rail insertion for chip-level pre-fabricated designFu-Wei Chen, Yi-Yu Liu. 308-311 [doi]
- Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioningMartin Trautmann, Stylianos Mamagkakis, Bruno Bougard, Jeroen Declerck, Erik Umans, Antoine Dejonghe, Liesbet Van der Perre, Francky Catthoor. 312-315 [doi]
- Fast and accurate protocol specific bus modeling using TLM 2.0H. W. M. van Moll, Henk Corporaal, VÃctor Reyes, Marleen Boonen. 316-319 [doi]
- Incorporating graceful degradation into embedded system designMichael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich. 320-323 [doi]
- Rewiring using IRredundancy Removal and AdditionChun-Chi Lin, Chun-Yao Wang. 324-327 [doi]
- Gate replacement techniques for simultaneous leakage and aging optimizationYu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. 328-333 [doi]
- Enabling concurrent clock and power gating in an industrial design flowLeticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino. 334-339 [doi]
- TRAM: A tool for Temperature and Reliability Aware Memory DesignAmin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir. 340-345 [doi]
- A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable ChipsMatteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis. 352-357 [doi]
- Communication minimization for in-network processing in body sensor networks: A buffer assignment techniqueHassan Ghasemzadeh, Nisha Jain, Marco Sgroi, Roozbeh Jafari. 358-363 [doi]
- A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standardLuca Larcher, Riccardo Brama, Marcello Ganzerli, Jacopo Iannacci, Marco Bedani, Antonio Gnudi. 364-368 [doi]
- Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharingJosé Ãngel DÃaz-Madrid, H. Neubauer, Hans Hauer, Ginés Doménech-Asensi, Ramó Ruiz-Merino. 369-373 [doi]
- PANEL SESSION - Is the second wave of HLS the one industry will surf on?Loic Le Toumelin. 374 [doi]
- Analyzing the impact of process variations on parametric measurements: Novel models and applicationsSherief Reda, Sani R. Nassif. 375-380 [doi]
- On linewidth-based yield analysis for nanometer lithographyAswin Sreedhar, Sandip Kundu. 381-386 [doi]
- Impact of voltage scaling on nanoscale SRAM reliabilityVikas Chandra, Robert C. Aitken. 387-392 [doi]
- A file-system-aware FTL design for flash-memory storage systemsPo-Liang Wu, Yuan-Hao Chang, Tei-Wei Kuo. 393-398 [doi]
- FSAF: File system aware flash translation layer for NAND Flash MemoriesSai Krishna Mylavarapu, Siddharth Choudhuri, Aviral Shrivastava, Jongeun Lee, Tony Givargis. 399-404 [doi]
- A set-based mapping strategy for flash-memory reliability enhancementYuan-Sheng Chu, Jen-Wei Hsieh, Yuan-Hao Chang, Tei-Wei Kuo. 405-410 [doi]
- Energy efficient multiprocessor task scheduling under input-dependent variationJason Cong, Karthik Gururaj. 411-416 [doi]
- Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scalingJungsoo Kim, Sungjoo Yoo, Chong-Min Kyung. 417-422 [doi]
- ORION 2.0: A fast and accurate NoC power and area model for early-stage design space explorationAndrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi. 423-428 [doi]
- PANEL SESSION - Open source hardware IP, are you serious?P. Parrish. 429 [doi]
- HOT TOPIC - Concurrent SoC development and end-to-end planningLorena Anghel. 430 [doi]
- Nano-electronics challenge chip designers meet real nano-electronics in 2010s?Shinobu Fujita. 431-432 [doi]
- MTJ-based nonvolatile logic-in-memory circuit, future prospects and issuesShoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu. 433-435 [doi]
- Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect TransistorsSubhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei. 436-441 [doi]
- Reconfigurable circuit design with nanomaterialsChen Dong, Scott Chilstedt, Deming Chen. 442-447 [doi]
- An architecture for secure software defined radioChunxiao Li, Anand Raghunathan, Niraj K. Jha. 448-453 [doi]
- Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storageXu Guo, Patrick Schaumont. 454-459 [doi]
- Hardware aging-based software meteringFoad Dabiri, Miodrag Potkonjak. 460-465 [doi]
- On-chip communication architecture exploration for processor-pool-based MPSoCYoung-Pyo Joo, Sungchan Kim, Soonhoi Ha. 466-471 [doi]
- Combined system synthesis and communication architecture exploration for MPSoCsMartin Lukasiewycz, Martin Streubühr, Michael Glaß, Christian Haubelt, Jürgen Teich. 472-477 [doi]
- UMTS MPSoC design evaluation using a system level design frameworkDouglas Densmore, Alena Simalatsar, Abhijit Davare, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli. 478-483 [doi]
- Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chipsMikael Väyrynen, Virendra Singh, Erik Larsson. 484-489 [doi]
- Improving yield and reliability of chip multiprocessorsAbhisek Pan, Omer Khan, Sandip Kundu. 490-495 [doi]
- A unified online Fault Detection scheme via checking of Stability ViolationGuihai Yan, Yinhe Han, Xiaowei Li. 496-501 [doi]
- Statistical fault injection: Quantified error and confidenceRégis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert. 502-506 [doi]
- KAST: K-associative sector translation for NAND flash memory in real-time systemsHyun-jin Cho, Dongkun Shin, Young Ik Eom. 507-512 [doi]
- White box performance analysis considering static non-preemptive software schedulingAlexander Viehl, Michael Pressler, Oliver Bringmann, Wolfgang Rosenstiel. 513-518 [doi]
- Application specific performance indicators for quantitative evaluation of the timing behavior for embedded real-time systemsFrank König, Dave Boers, Frank Slomka, Ulrich Margull, Michael Niemetz, Gerhard Wirrer. 519-523 [doi]
- Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resourcesMircea Negrean, Simon Schliecker, Rolf Ernst. 524-529 [doi]
- Light NUCA: A proposal for bridging the inter-cache latency gapDarÃo Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, VÃctor Viñals. 530-535 [doi]
- ReSim, a trace-driven, reconfigurable ILP processor simulatorSotiria Fytraki, Dionisios N. Pnevmatikatos. 536-541 [doi]
- Heterogeneous coarse-grained processing elements: A template architecture for embedded processing accelerationGiovanni Ansaloni, Paolo Bonzini, Laura Pozzi. 542-547 [doi]
- Algorithms for the automatic extension of an instruction-setCarlo Galuzzi, Dimitris Theodoropoulos, Roel Meeuws, Koen Bertels. 548-553 [doi]
- Dimensioning heterogeneous MPSoCs via parallelism analysisBastian Ristau, Torsten Limberg, Oliver Arnold, Gerhard Fettweis. 554-557 [doi]
- MPSoCs run-time monitoring through Networks-on-ChipLeandro Fiorin, Gianluca Palermo, Cristina Silvano. 558-561 [doi]
- Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraintsDaniele Ludovici, Francisco Gilabert Villamón, Simone Medardoni, CrispÃn Gómez Requena, MarÃa Engracia Gómez, Pedro López, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi. 562-565 [doi]
- A hybrid packet-circuit switched on-chip network based on SDMMehdi Modarressi, Hamid Sarbazi-Azad, Mohammad Arjomand. 566-569 [doi]
- SecBus: Operating System controlled hierarchical page-based memory bus protectionLifeng Su, Stephan Courcambeck, Pierre Guillemin, Christian Schwarz, Renaud Pacalet. 570-573 [doi]
- A link arbitration scheme for quality of service in a latency-optimized network-on-chipJonas Diemer, Rolf Ernst. 574-577 [doi]
- Flow regulation for on-chip communicationZhonghai Lu, Mikael Millberg, Axel Jantsch, Alistair C. Bruce, Pieter van der Wolf, Tomas Henriksson. 578-581 [doi]
- Customizing IP cores for system-on-chip designs using extensive external don t-caresKai-Hui Chang, Valeria Bertacco, Igor L. Markov. 582-585 [doi]
- Extending IP-XACT to support an MDE based approach for SoC designAmin El Mrabti, Frédéric Pétrot, Aimen Bouchhima. 586-589 [doi]
- Overcoming limitations of the SystemC data introspectionChristian Genz, Rolf Drechsler. 590-593 [doi]
- Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakageHao Xu, Ranga Vemuri, Wen-Ben Jone. 594-597 [doi]
- A power-efficient migration mechanism for D-NUCA cachesAlessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete. 598-601 [doi]
- Panel Session - Vertical integration versus disaggregationYervant Zorian. 602 [doi]
- System-level process variability analysis and mitigation for 3D MPSoCsSiddharth Garg, Diana Marculescu. 604-609 [doi]
- Co-design of signal, power, and thermal distribution networks for 3D ICsYoung-Joon Lee, Yoon Jo Kim, Gang Huang, Muhannad Bakir, Yogendra Joshi, Andrei Fedorov, Sung Kyu Lim. 610-615 [doi]
- Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesisShashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli. 616-621 [doi]
- Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesisM. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli. 622-627 [doi]
- Enhancing correlation electromagnetic attack using planar near-field cartographyDenis Réal, Frédéric Valette, M hamed Drissi. 628-633 [doi]
- Evaluation on FPGA of triple rail logic robustness against DPA and DEMAVictor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans. 634-639 [doi]
- Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraintsLaurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar. 640-645 [doi]
- Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPTLuca Henzen, Flavio Carbognani, Norbert Felber, Wolfgang Fichtner. 646-651 [doi]
- Architectural support for low overhead detection of memory violationsSaugata Ghose, Latoya Gilgeous, Polina Dudnik, Aneesh Aggarwal, Corey Waxman. 652-657 [doi]
- Caspar: Hardware patching for multicore processorsIlya Wagner, Valeria Bertacco. 658-663 [doi]
- A new speculative addition architecture suitable for two s complement operationsAlessandro Cilardo. 664-669 [doi]
- Limiting the number of dirty cache linesPepijn J. de Langen, Ben H. H. Juurlink. 670-675 [doi]
- Contactless testing: Possibility or pipe-dream?Erik Jan Marinissen, Dae-Young Lee, John P. Hayes, Chris Sellathamby, Brian Moore, Steven Slupsky, Laurence Pujol. 676-681 [doi]
- Analysis and optimization of fault-tolerant embedded systems with hardened processorsViacheslav Izosimov, Ilia Polian, Paul Pop, Petru Eles, Zebo Peng. 682-687 [doi]
- On bounding response times under software transactional memory in distributed multiprocessor real-time systemsSherif Fadel Fahmy, Binoy Ravindran, E. Douglas Jensen. 688-693 [doi]
- An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systemsChuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo, Lothar Thiele. 694-699 [doi]
- A graph grammar based approach to automated multi-objective analog circuit designAngan Das, Ranga Vemuri. 700-705 [doi]
- Massively multi-topology sizing of analog integrated circuitsPieter Palmers, Trent McConaghy, Michiel Steyaert, Georges G. E. Gielen. 706-711 [doi]
- Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuitsSawal Ali, Li Ke, Reuben Wilcock, Peter Wilson. 712-717 [doi]
- Computation of IP3 using single-tone moments analysisDani Tannir, Roni Khazaka. 718-723 [doi]
- Formal approaches to analog circuit verificationErich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang. 724-729 [doi]
- Panel session - ESL methodology for SoCLarry Toda, Walden C. Rhines. 730 [doi]
- An overview of non-volatile memory technology and the implication for tools and architecturesHai Li, Yiran Chen. 731-736 [doi]
- Power and performance of read-write aware Hybrid Caches with non-volatile memoriesXiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yuan Xie. 737-742 [doi]
- Using non-volatile memory to save energy in serversDavid Roberts, Taeho Kgil, Trevor N. Mudge. 743-748 [doi]
- aEqualized: A novel routing algorithm for the Spidergon Network On ChipNicola Concer, Salvatore Iamundo, Luciano Bononi. 749-754 [doi]
- Group-caching for NoC based multicore cache coherent systemsWang Zuo, Shi Feng, Zuo Qi, Ji Weixing, Li Jiaxin, Deng Ning, Xue Licheng, Tan Yuan, Qiao Baojun. 755-760 [doi]
- A monitor interconnect and support subsystem for multicore processorsSailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Russell Tessier. 761-766 [doi]
- A real-time application design methodology for MPSoCsGiovanni Beltrame, Luca Fossati, Donatella Sciuto. 767-772 [doi]
- Adaptive prefetching for shared cache based chip multiprocessorsMahmut T. Kandemir, Yuanrui Zhang, Ozcan Ozturk. 773-778 [doi]
- CUFFS: An instruction count based architectural framework for security of MPSoCsKrutartha Patel, Sri Parameswaran, Roshan G. Ragel. 779-784 [doi]
- Design as you see FIT: System-level soft error analysis of sequential circuitsDaniel Holcomb, Wenchao Li, Sanjit A. Seshia. 785-790 [doi]
- Detecting errors using multi-cycle invariance informationNuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar. 791-796 [doi]
- A novel approach to entirely integrate Virtual Test into test development flowPing Lu, Daniel Glaser, Gürkan Uygur, Klaus Helmreich. 797-802 [doi]
- Robust non-preemptive hard real-time scheduling for clustered multicore platformsMichele Lombardi, Michela Milano, Luca Benini. 803-808 [doi]
- Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchyAndrea Marongiu, Luca Benini. 809-814 [doi]
- Using randomization to cope with circuit uncertaintyHamid Safizadeh, Mohammad Tahghighi, Ehsan K. Ardestani, Gholamhossein Tavasoli, Kia Bazargan. 815-820 [doi]
- Process variation aware thread mapping for Chip MultiprocessorsShengyan Hong, Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk. 821-826 [doi]
- Gate sizing for large cell-based designsStephan Held. 827-832 [doi]
- Multi-domain clock skew scheduling-aware register placement to optimize clock distribution networkNaser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani. 833-838 [doi]
- Decoupling capacitor planning with analytical delay model on RLC power gridYe Tao, Sung Kyu Lim. 839-844 [doi]
- Package routability- and IR-drop-aware finger/pad assignment in chip-package co-designChao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih. 845-850 [doi]
- Learning early-stage platform dimensioning from late-stage timing verificationKai Richter, Marek Jersak, Rolf Ernst. 851-857 [doi]
- The influence of real-time constraints on the design of FlexRay-based systemsStephan Reichelt, Oliver Scheickl, Gökhan Tabanoglu. 858-863 [doi]
- Time and memory tradeoffs in the implementation of AUTOSAR componentsAlberto Ferrari, Marco Di Natale, Giacomo Gentile, Giovanni Reggiani, Paolo Gai. 864-869 [doi]
- Systolic like soft-detection architecture for 4×4 64-QAM MIMO systemPankaj Bhagawat, Rajballav Dash, Gwan Choi. 870-873 [doi]
- Co-simulation based platform for wireless protocols design explorationsAlain Fourmigue, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid. 874-877 [doi]
- How to speed-up your NLFSR-based stream cipherElena Dubrova. 878-881 [doi]
- A high performance reconfigurable Motion Estimation hardware architectureOzgur Tasdizen, Halil Kukner, Abdulkadir Akin, Ilker Hamzaoglu. 882-885 [doi]
- Partition-based exploration for reconfigurable JPEG designsPhilip G. Potter, Wayne Luk, Peter Y. K. Cheung. 886-889 [doi]
- Automated synthesis of streaming C applications to process networks in hardwareSven van Haastregt, Bart Kienhuis. 890-893 [doi]
- Distributed sensor for steering wheel rip force measurement in driver fatigue detectionFederico Baronti, Francesco Lenzi, Roberto Roncella, Roberto Saletti. 894-897 [doi]
- Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancySaturnino Garcia, Alex Orailoglu. 898-901 [doi]
- Machine learning-based volume diagnosisSeongmoon Wang, Wenlong Wei. 902-905 [doi]
- Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-ChipFrancesco Paterna, Luca Benini, Andrea Acquaviva, Francesco Papariello, Giuseppe Desoli, Mauro Olivieri. 906-909 [doi]
- Panel session - Architectures and integration for programmable SoC sGuido Schreiner, Endric Schubert. 910 [doi]
- Process Variation Aware SRAM/Cache for aggressive voltage-frequency scalingAvesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi. 911-916 [doi]
- Single ended 6T SRAM with isolated read-port for low-power embedded systemsJawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew. 917-922 [doi]
- System-level power/performance evaluation of 3D stacked DRAMs for mobile applicationsMarco Facchini, Trevor Carlson, Anselme Vignon, Martin Palkovic, Francky Catthoor, Wim Dehaene, Luca Benini, Paul Marchal. 923-928 [doi]
- A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect contextAnselme Vignon, Stefan Cosemans, Wim Dehaene, Pol Marchal, Marco Facchini. 929-933 [doi]
- A case for multi-channel memories in video recordingEero Aho, Jari Nikara, Petri A. Tuominen, Kimmo Kuusilinna. 934-939 [doi]
- High level H.264/AVC video encoder parallelization for multiprocessor implementationHajer K. Zrida, Abderrazek Jemai, Ahmed C. Ammari, Mohamed Abid. 940-945 [doi]
- Temperature-aware scheduler based on thermal behavior grouping in multicore systemsInchoon Yeo, Eun Jung Kim. 946-951 [doi]
- Hardware/software co-design architecture for thermal management of chip multiprocessorsOmer Khan, Sandip Kundu. 952-957 [doi]
- Cross-architectural design space exploration tool for reconfigurable processorsLars Bauer, Muhammad Shafique, Jörg Henkel. 958-963 [doi]
- Automatically mapping applications to a self-reconfiguring platformKarel Bruneel, Fatma Abouelella, Dirk Stroobandt. 964-969 [doi]
- OSSS+R: A framework for application level modelling and synthesis of reconfigurable systemsAndreas Schallenberg, Wolfgang Nebel, Andreas Herrholz, Philipp A. Hartmann, Frank Oppenheimer. 970-975 [doi]
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