Abstract is missing.
- Leakage power: trends, analysis and avoidanceDavid Blaauw, Anirudh Devgan, Farid N. Najm. [doi]
- The development of integrated circuit industry in ChinaZhenghua Jiang. [doi]
- Panel III: EDA market in ChinaDavid Chen, Nancy Wu, Wayne Dai, Jun Tan, Weiping Liu, Hao Min, Jian Yue Pan. [doi]
- Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen. [doi]
- Design at the end of the silicon roadmapJan M. Rabaey. [doi]
- Silicon compilation: the answer to reducing IC development costsRajeev Madhavan. [doi]
- Embedded tutorial I: design for manufacturabilityVijay Pitchumani. [doi]
- Are we ready for system-level synthesis?Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe. [doi]
- Challenges to covering the high-level to silicon gapBill Grundmann. 1 [doi]
- TERPS: the embedded reliable processing systemHongxia Wang, Samuel Rodríguez, Cagdas Dirik, Amol Gole, Vincent Chan, Bruce Jacob. 1-2 [doi]
- The polygonal contraction heuristic for rectilinear Steiner tree constructionYin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan. 1-6 [doi]
- Designing reliable circuit in the presence of soft errorsNarayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. 1 [doi]
- Opportunities and challenges for better than worst-case designTodd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge. 2-7 [doi]
- AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flowDimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, K. Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis. 3-4 [doi]
- Standard ::::CMOS:::: technology on-chip inductors with ::::pn:::: junctions substrate isolationHongyan Jian, Zhangwen Tang, Jie He, Jinglan He, Min Hao. 5-6 [doi]
- A bandwidth efficient subsampling-based block matching architecture for motion estimationHao-Yun Chin, Chao-Chung Cheng, Yu-Kun Lin, Tian-Sheuan Chang. 7-8 [doi]
- An-OARSMan: obstacle-avoiding routing tree construction with good length performanceYu Hu, Tong Jing, Xianlong Hong, Zhe Feng 0002, Xiaodong Hu, Guiying Yan. 7-12 [doi]
- Microarchitecture evaluation with floorplanning and interconnect pipeliningAshok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong. 8-15 [doi]
- Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS processAkinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera. 9-10 [doi]
- A design of high speed double precision floating point adder using macro modulesChi Huang, Xinyu Wu, Jinmei Lai, Chengshou Sun, Gang Li. 11-12 [doi]
- A low-power video segmentation LSI with boundary-active-only architectureTakashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch. 13-14 [doi]
- Making fast buffer insertion even faster via approximation techniquesZhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi. 13-18 [doi]
- The design and implementation of a DVB receiving chip with PCI interfaceXu Ningyi, Li Shaohua, Yu Wei, He Guanghui, Zhang Hao, Luo Fei, Zhou Zucheng. 15-16 [doi]
- Design and implementation of an SDH high-speed switchDehui Zhang, Quan Liang Zhao, Jun Gang Han. 17-18 [doi]
- Concurrent flip-flop and buffer insertion with adaptive blockage avoidanceZhong-Ching Lu, Ting-Chi Wang. 19-22 [doi]
- Design of vehicle position tracking system using short message services and its implementation on FPGAArias Tanti Hapsari, Eniman Y. Syamsudin, Imron Pramana. 19-20 [doi]
- Design of A 2.4-GHz integrated frequency synthesizerFei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun. 21-22 [doi]
- Buffering global interconnects in structured ASIC designTianpei Zhang, Sachin S. Sapatnekar. 23-26 [doi]
- An improved test access mechanism structure and optimization technique in system-on-chipFeng Jianhua, Long Jieyi, Xu Wenhua, Ye Hongfei. 23-24 [doi]
- Mapping and physical planning of networks-on-chip architectures with quality-of-service guaranteesSrinivasan Murali, Luca Benini, Giovanni De Micheli. 27-32 [doi]
- Time and energy efficient mapping of embedded applications onto NoCsCésar A. M. Marcon, André Borin Suarez, Altamiro Amadeu Susin, Luigi Carro, Flávio Rech Wagner. 33-38 [doi]
- Communication-driven task binding for multiprocessor with latency insensitive network-on-chipLiang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou. 39-44 [doi]
- System-level communication modeling for network-on-chip synthesisAndreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski. 45-48 [doi]
- MAIA: a framework for networks on chip generation and verificationLuciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes, Ney Calazans. 49-52 [doi]
- Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional codeYinhe Han, Yu Hu, Huawei Li, Xiaowei Li. 53-58 [doi]
- Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxationYasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty. 59-64 [doi]
- Testing comparison faults of ternary CAMs based on comparison faults of binary CAMsJin-Fu Li. 65-70 [doi]
- SPIN-PAC: test compaction for speed-independent circuitsFeng Shi, Yiorgos Makris. 71-74 [doi]
- A Huffman-based coding with efficient test applicationMichihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue. 75-78 [doi]
- ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stressRouying Zhan, Haolu Xie, Haigang Feng, Albert Z. Wang. 79-82 [doi]
- A new method for model based frugal OPCXiaolang Yan, Ye Chen, Zheng Shi, Yue Ma. 83-86 [doi]
- Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-upYong Zhan, Sachin S. Sapatnekar. 87-92 [doi]
- Analysis of buffered hybrid structured clock networksYi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan. 93-98 [doi]
- Clock network minimization methodology based on incremental placementLiang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu. 99-102 [doi]
- A multi-level transmission line network approach for multi-giga hertz clock distributionHongyu Chen, Chung-Kuan Cheng. 103-106 [doi]
- Gibbs sampling in power grid analysisZhixin Tian, Huazhong Yang, Rong Luo. 107-110 [doi]
- A wideband hierarchical circuit reduction for massively coupled interconnectsHao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan. 111-114 [doi]
- A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing ProblemTong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He. 115-120 [doi]
- Thermal-driven multilevel routing for 3-D ICsJason Cong, Yan Zhang. 121-126 [doi]
- Wave-pipelined on-chip global interconnectLizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen. 127-132 [doi]
- Evaluation of on-chip transmission line interconnect using wire length distributionJunpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu. 133-138 [doi]
- A formalism for functionality preserving system level transformationsSamar Abdi, Daniel Gajski. 139-144 [doi]
- Embedded software generation from system level specification for multi-tasking embedded systemsKiSeun Kwon, Youngmin Yi, Dohyung Kim, Soonhoi Ha. 145-150 [doi]
- Scheduler implementation in MP SoC designYoungchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya. 151-156 [doi]
- Optimizing embedded applications using programmer-inserted hintsG. Chen, Mahmut T. Kandemir. 157-160 [doi]
- Static analysis and automatic code synthesis of flexible FSM modelDohyung Kim, Soonhoi Ha. 161-165 [doi]
- Constraint extraction for pseudo-functional scan-based delay testingYung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Cheng. 166-171 [doi]
- Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLAHafizur Rahaman, Debesh K. Das. 172-177 [doi]
- Propagation delay fault: a new fault model to test delay faultsXijiang Lin, Janusz Rajski. 178-183 [doi]
- Oscillation ring based interconnect test scheme for SOCKatherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen. 184-187 [doi]
- Bridging fault testability of BDD circuitsJunhao Shi, Görschwin Fey, Rolf Drechsler. 188-191 [doi]
- Yield driven gate sizing for coupling-noise reduction under uncertaintyDebjit Sinha, Hai Zhou. 192-197 [doi]
- Maze routing with OPC considerationYun-Ru Wu, Ming-Chao Tsai, Ting-Chi Wang. 198-203 [doi]
- Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithmMasahiro Murakawa, Mitiko Miura-Mattausch, Tetsuya Higuchi. 204-207 [doi]
- Substrate resistance extraction with direct boundary element methodXiren Wang, Wenjian Yu, Zeyi Wang. 208-211 [doi]
- An efficient combinationality check technique for the synthesis of cyclic combinational circuitsVineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang. 212-215 [doi]
- Library cell layout with Alt-PSM compliance and composabilityKe Cao, Puneet Dhawan, Jiang Hu. 216-219 [doi]
- Forward discrete probability propagation method for device performance characterization under process variationsRasit Onur Topaloglu, Alex Orailoglu. 220-223 [doi]
- Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reductionZhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He. 224-229 [doi]
- Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagramsHuiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen. 230-235 [doi]
- A new approach for ring oscillator simulation using the harmonic balance methodXiaochun Duan, Kartikeya Mayaram. 236-239 [doi]
- Efficient transient simulation for transistor-level analysisZhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh. 240-243 [doi]
- Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuitsBang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles Chiang, Dian Zhou. 244-249 [doi]
- Block based statistical timing analysis with extended canonical timing modelLizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen. 250-253 [doi]
- FSM re-engineering and its application in low power state encodingLin Yuan, Gang Qu, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli. 254-259 [doi]
- Post-layout logic duplication for synthesis of domino circuits with complex gatesAiqun Cao, Ruibing Lu, Cheng-Kok Koh. 260-265 [doi]
- Detecting support-reducing bound sets using two-cofactor symmetriesJin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch. 266-271 [doi]
- Synthesis of quantum logic circuitsVivek V. Shende, Stephen S. Bullock, Igor L. Markov. 272-275 [doi]
- STACCATO: disjoint support decompositions from BDDs through symbolic kernelsStephen Plaza, Valeria Bertacco. 276-279 [doi]
- A framework for automated and optimized ASIP implementation supporting multiple hardware description languagesOliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel. 280-285 [doi]
- A processor core synthesis system in IP-based SoC designNaoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 286-291 [doi]
- Speed and voltage selection for GALS systems based on voltage/frequency islandsKoushik Niyogi, Diana Marculescu. 292-297 [doi]
- A system-level approach to hardware reconfigurable systemsChristian Haubelt, Stephan Otto, Cornelia Grabbe, Jürgen Teich. 298-301 [doi]
- High-level synthesis for DSP applications using heterogeneous functional unitsZili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha. 302-304 [doi]
- Evaluation of the statistical delay quality modelYasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara. 305-310 [doi]
- Fault tolerant nanoelectronic processor architecturesWenjing Rao, Alex Orailoglu, Ramesh Karri. 311-316 [doi]
- An efficient control-oriented coverage metricShireesh Verma, Kiran Ramineni, Ian G. Harris. 317-322 [doi]
- An observability measure to enhance statement coverage metric for proper evaluation of verification completenessTai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou. 323-326 [doi]
- Tightly integrate dynamic verification with formal verification: a GSTE based approachJin Yang, Avi Puder. 327-330 [doi]
- On structure and suboptimality in placementSatoshi Ono, Patrick H. Madden. 331-336 [doi]
- Optimal placement by branch-and-pricePradeep Ramachandaran, Ameya R. Agnihotri, Satoshi Ono, Purushothaman Damodaran, Krishnaswami Srihari, Patrick H. Madden. 337-342 [doi]
- Detailed placement for improved depth of focus and CD controlPuneet Gupta, Andrew B. Kahng, Chul-Hong Park. 343-348 [doi]
- Floorplan management: incremental placement for gate sizing and buffer insertionChen Li 0004, Cheng-Kok Koh, Patrick H. Madden. 349-354 [doi]
- Low-power techniques for network security processorsYi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu. 355-360 [doi]
- A configurable AES processor for enhanced securityChih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu. 361-366 [doi]
- Power estimation starategies for a low-power security processorYen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang. 367-371 [doi]
- Design and test of a scalable security processorChih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu. 372-375 [doi]
- System-level design space exploration for security processor prototyping in analytical approachesYung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee. 376-380 [doi]
- Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian RelaxationHsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen. 381-386 [doi]
- Effective analytical delay model for transistor sizingZhaojun Wo, Israel Koren. 387-392 [doi]
- Achieving continuous V::T:: performance in a dual V::T:: processKanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan. 393-398 [doi]
- Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignmentDongwoo Lee, David Blaauw, Dennis Sylvester. 399-404 [doi]
- Floorplanning for 3-D VLSI designLei Cheng, Liang Deng, Martin D. F. Wong. 405-411 [doi]
- Optimal redistribution of white space for wire length minimizationXiaoping Tang, Ruiqi Tian, Martin D. F. Wong. 412-417 [doi]
- Crowdedness-balanced multilevel partitioning for uniform resource utilizationYongseok Cheon, Martin D. F. Wong. 418-423 [doi]
- Partitioning and placement for buildable QCA circuitsRamprasad Ravichandran, Michael T. Niemier, Sung Kyu Lim. 424-427 [doi]
- PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduitsChanseok Hwang, Massoud Pedram. 428-431 [doi]
- MUP: a minimal unsatisfiability proverJinbo Huang. 432-437 [doi]
- Integration of supercubing and learning in a SAT solverDomagoj Babic, Alan J. Hu. 438-444 [doi]
- Dynamic symmetry-breaking for improved Boolean optimizationFadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah. 445-450 [doi]
- A fast counterexample minimization approach with refutation analysis and incremental SATShengYu Shen, Ying Qin, Sikun Li. 451-454 [doi]
- Sequential equivalence checking using cutsWei Huang, PuShan Tang, Min Ding. 455-458 [doi]
- Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noiseXiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury. 459-464 [doi]
- Hierarchical analysis of process variation for mixed-signal systemsFang Liu, Sule Ozev. 465-470 [doi]
- A novel wavelet method for noise analysis of nonlinear circuitsXuan Zeng, Bank Liu, Jun Tao, Charles Chiang, Dian Zhou. 471-476 [doi]
- An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodelsMengmeng Ding, Glenn Wolfe, Ranga Vemuri. 477-482 [doi]
- Partial reluctance based circuit simulation is efficient and stableYu Du, Wayne Dai. 483-488 [doi]
- SAGA: synthesis technique for guaranteed throughput NoC architecturesKrishnan Srinivasan, Karam S. Chatha. 489-494 [doi]
- Automated throughput-driven synthesis of bus-based communication architecturesSudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane. 495-498 [doi]
- Simulation acceleration of transaction-level models for SoC with RTL sub-blocksJae-Gon Lee, Wooseung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung. 499-502 [doi]
- Statistical modeling of cross-coupling effects in VLSI interconnectsMridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw. 503-506 [doi]
- Compact and stable modeling of partial inductance and reluctance matricesHong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong. 507-510 [doi]
- Scalable interprocedural register allocation for high level synthesisRami Beidas, Jianwen Zhu. 511-516 [doi]
- Simultaneous floorplanning and resource binding: a probabilistic approachAzadeh Davoodi, Ankur Srivastava. 517-522 [doi]
- Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressionsAnup Hosangadi, Farzan Fallah, Ryan Kastner. 523-528 [doi]
- A fast algorithm for finding common multiple-vertex dominators in circuit graphsRené Krenz, Elena Dubrova. 529-532 [doi]
- Low-power domino circuits using NMOS pull-up on off-critical pathsAbdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh. 533-538 [doi]
- Low-leakage robust SRAM cell design for sub-100nm technologiesShengqi Yang, Wayne Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie. 539-544 [doi]
- Studying interactions between prefetching and cache line turnoffIsmail Kadayif, Mahmut T. Kandemir, Guilin Chen. 545-548 [doi]
- The development of high performance FFT IP cores through hybrid low power algorithmic methodologyWei Han, Ahmet T. Erdogan, Tughrul Arslan, M. Hasan. 549-552 [doi]
- Battery-aware instruction generation for embedded processorsNewton Cheung, Sri Parameswaran, Jörg Henkel. 553-556 [doi]
- A variation-aware low-power coding methodology for tightly coupled busesMasanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura. 557-560 [doi]
- Automatic assume guarantee analysis for assertion-based formal verificationDong Wang, Jeremy R. Levitt. 561-566 [doi]
- TED+: a data structure for microprocessor verificationPejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi. 567-572 [doi]
- Improved Boolean function hashing based on multiple-vertex dominatorsRené Krenz, Elena Dubrova. 573-578 [doi]
- Lower bounds for dynamic BDD reorderingRüdiger Ebendt, Rolf Drechsler. 579-582 [doi]
- Partitioned model checking from software specificationsXiushan Feng, Alan J. Hu, Jin Yang. 583-587 [doi]
- Register placement for low power clock networkYongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu. 588-593 [doi]
- Skew scheduling and clock routing for improved tolerance to process variationsGanesh Venkataraman, Cliff C. N. Sze, Jiang Hu. 594-599 [doi]
- Stability analysis of active clock deskewing systems using a control theoretic approachVinil Varghese, Tom Chen, Peter Young. 600-605 [doi]
- Process variation robust clock tree routingWai-Ching Douglas Lam, Cheng-Kok Koh. 606-611 [doi]
- IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systemsNacer-Eddine Zergainoh, Katalin Popovici, Ahmed Amine Jerraya, Pascal Urard. 612-618 [doi]
- A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessingKazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera. 619-622 [doi]
- An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVCLingfeng Li, Satoshi Goto, Takeshi Ikenaga. 623-626 [doi]
- A new register file access architecture for software pipelining in VLIW processorsYanjun Zhang, Hu He, Yihe Sun. 627-630 [doi]
- A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264Minho Kim, Ingu Hwang, Soo-Ik Chae. 631-634 [doi]
- Automatic synthesis and scheduling of multirate DSP algorithmsYing Yi, Mark Milward, Sami Khawam, Ioannis Nousias, Tughrul Arslan. 635-638 [doi]
- A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machinesZhenyu Liu, Tughrul Arslan, Sami Khawam, Iain Lindsay. 639-644 [doi]
- Routing track duplication with fine-grained power-gating for FPGA interconnect power reductionYan Lin, Fei Li, Lei He. 645-650 [doi]
- Exploiting temporal idleness to reduce leakage power in programmable architecturesRajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia. 651-656 [doi]
- Methodology for high level estimation of FPGA power consumptionVijay Degalahal, Tim Tuan. 657-660 [doi]
- Leakage control in FPGA routing fabricSuresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan. 661-664 [doi]
- A 1GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversionK. Praveen Jayakar Thomas, Ram Singh Rana, Yong Lian. 665-670 [doi]
- An elitist distributed particle swarm algorithm for RF IC optimizationMin Chu, David J. Allstot. 671-674 [doi]
- Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimizationMin Chu, David J. Allstot. 675-678 [doi]
- A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technologyMiao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao. 679-682 [doi]
- A dynamic reconfigurable RF circuit architectureKenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu. 683-686 [doi]
- Prediction of LC-VCOs tuning curves with period calculation techniqueZhangwen Tang, Jie He, Hongyan Jian, Haiqing Zhang, Jie Zhang, Hao Min. 687-690 [doi]
- Hardware/software partitioning for platform-based design methodZhihui Xiong, Jihua Chen, Sikun Li. 691-696 [doi]
- Abstracting functionality for modular performance analysis of hard real-time systemsErnesto Wandeler, Lothar Thiele. 697-702 [doi]
- Optimizing intra-task voltage scheduling using data flow analysisDongkun Shin, Jihong Kim. 703-708 [doi]
- FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detectionJohn Conner, Yuan Xie, Mahmut T. Kandemir, Robert Dick, Greg M. Link. 709-712 [doi]
- Compiler-directed selective data protection against soft errorsG. Chen, Mahmut T. Kandemir, Mary Jane Irwin, Gokhan Memik. 713-716 [doi]
- A perturbation-aware noise convergence methodology for high frequency microprocessorsPrashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda. 717-722 [doi]
- Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversionTakashi Sato, Masanori Hashimoto, Hidetoshi Onodera. 723-728 [doi]
- A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor busesRaid Ayoub, Alex Orailoglu. 729-734 [doi]
- VLSI on-chip power/ground network optimization considering decap leakage currentsJingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan. 735-738 [doi]
- Probabilistic congestion model considering shielding for crosstalk reductionJinjun Xiong, Lei He. 739-742 [doi]
- Customized on-chip memories for embedded chip multiprocessorsOzcan Ozturk, Mahmut T. Kandemir, G. Chen, Mary Jane Irwin, Mustafa Karaköy. 743-748 [doi]
- Performance driven reliable link design for networks on chipsRutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli. 749-754 [doi]
- Dynamic power management using on demand paging for networked embedded systemsYuvraj Agarwal, Curt Schurgers, Rajesh Gupta. 755-759 [doi]
- An FPGA implementation of low-density parity-check code decoder with multi-rate capabilityLei Yang, Manyuan Shen, Hui Liu, C.-J. Richard Shi. 760-763 [doi]
- Single-track asynchronous pipeline controller designXiao Yong, Zhou Runde. 764-768 [doi]
- Using data replication to reduce communication energy on chip multiprocessorsMahmut T. Kandemir, Guangyu Chen, Feihui Li, I. Demirkiran. 769-772 [doi]
- Three-dimensional place and route for FPGAsCristinel Ababei, Hushrav Mogal, Kia Bazargan. 773-778 [doi]
- Modern FPGA constrained placementWai-Kei Mak. 779-784 [doi]
- Clustering techniques for coarse-grained, antifuse FPGAsChang Woo Kang, Massoud Pedram. 785-790 [doi]
- A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAsVivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti. 791-794 [doi]
- Resource sharing in pipelined CDFG synthesisSomsubhra Mondal, Seda Ogrenci Memik. 795-798 [doi]
- A 2.4-GHz linear-tuning CMOS LC voltage-controlled oscillatorHong Zhang, Guican Chen, Ning Li. 799-802 [doi]
- Adiabatic CMOS gate and adiabatic circuit design for low-power applicationsGuoqiang Hang. 803-808 [doi]
- An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing systemOsamu Matsumoto, Hisashi Harada, Yasuo Morimoto, Toshio Kumamoto, Takahiro Miki, Masao Hotta. 809-814 [doi]
- A class D audio power amplifier with high-efficiency and low-distortionChen Hai, Wu Xiaobo. 815-818 [doi]
- Substrate noise modeling in early floorplanning of MS-SOCsGrzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang. 819-823 [doi]
- Instruction scheduling of VLIW architectures for balanced power consumptionShu Xiao, Edmund Ming-Kit Lai. 824-829 [doi]
- Power minimization techniques on distributed real-time systems by global and local slack managementShaoxiong Hua, Gang Qu. 830-835 [doi]
- A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processorsJaewon Seo, Nikil D. Dutt. 836-841 [doi]
- A dynamic voltage scaling algorithm for energy reduction in hard real-time systemsVan R. Culver, Sunil P. Khatri. 842-845 [doi]
- An efficient dynamic task scheduling algorithm for battery powered DVS systemsJianli Zhuo, Chaitali Chakrabarti. 846-849 [doi]
- Optimal module and voltage assignment for low-powerDeming Chen, Jason Cong, Junjuan Xu. 850-855 [doi]
- Bitwidth-aware scheduling and binding in high-level synthesisJason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng. 856-861 [doi]
- Functionality directed clustering for low power MTCMOS designTsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu. 862-867 [doi]
- Wake-up protocols for controlling current surges in MTCMOS-based technologyAzadeh Davoodi, Ankur Srivastava. 868-871 [doi]
- On multiple-voltage high-level synthesis using algorithmic transformationsHsueh-Chih Yang, Lan-Rong Dung. 872-876 [doi]
- An advanced bit-line clamping scheme in magnetic RAM for wide sensing marginJong-Chul Lim, Hye-Seung Yu, Jae-Suk Choi, Soo-Won Kim. 877-882 [doi]
- Constructing zero-deficiency parallel prefix adder of minimum depthHaikun Zhu, Chung-Kuan Cheng, Ronald L. Graham. 883-888 [doi]
- An accurate 1.08-GHz CMOS LC voltage-controlled oscillatorZhangwen Tang, Jie He, Hongyan Jian, Hao Min. 889-892 [doi]
- Area-IO DRAM/logic integration with system-in-a-package (SiP)Anru Wang, Wayne Wei-Ming Dai. 893-896 [doi]
- Design of an efficient memory subsystem for network processorShuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li. 897-900 [doi]
- Design of clocked circuits using UMLZhenxin Sun, Weng-Fai Wong, Yongxin Zhu, Santhosh Kumar Pilakkat. 901-904 [doi]
- A function generator-based reconfigurable systemVivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti. 905-909 [doi]
- Crossbar based design schemes for switch boxes and programmable interconnection networksHongbing Fan, Yu-Liang Wu. 910-915 [doi]
- A domain specific reconfigurable Viterbi fabric for system-on-chip applicationsCheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay. 916-919 [doi]
- Design of a high performance FFT processor based on FPGAChu Chao, Zhang Qin, Xie Yingke, Han Chengde. 920-923 [doi]
- Increasing FPGA resilience against soft errors using task duplicationGuangyu Chen, Feihui Li, Mahmut T. Kandemir, I. Demirkiran. 924-927 [doi]
- Automatic extraction of function bodies from software binariesGaurav Mittal, David Zaretsky, Gokhan Memik, Prith Banerjee. 928-931 [doi]
- Modeling SystemC design in UML and automatic code generationChen Xi, Lu JianHua, Zhou Zucheng, Shang YaoHui. 932-935 [doi]
- Enabling RTOS simulation modeling in a system level design languageM. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. 936-939 [doi]
- A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systemsGiuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti. 940-943 [doi]
- Multi-metric and multi-entity characterization of applications for early system design explorationLukai Cai, Andreas Gerstlauer, Daniel Gajski. 944-947 [doi]
- An integrated performance and power model for superscalar processor designsYongxin Zhu, Weng-Fai Wong, Stefan Andrei. 948-951 [doi]
- Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platformsZhe Ma, Francky Catthoor, Johan Vounckx. 952-955 [doi]
- A flexible framework for communication evaluation in SoC designPraveen Kalla, Xiaobo Sharon Hu, Jörg Henkel. 956-959 [doi]
- Feasibility analysis of messages for on-chip networks using wormhole routingZhonghai Lu, Axel Jantsch, Ingo Sander. 960-964 [doi]
- A clustering technique to optimize hardware/software synchronizationJunyu Peng, Samar Abdi, Daniel Gajski. 965-968 [doi]
- Using abstract CPU subsystem simulation model for high level HW/SW architecture explorationAimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya. 969-972 [doi]
- On combining iteration space tiling with data space tiling for scratch-pad memory systemsChunhui Zhang, Fadi J. Kurdahi. 973-976 [doi]
- REMIC: design of a reactive embedded microprocessor coreZoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari. 977-981 [doi]
- Online hardware/software partitioning in networked embedded systemsThilo Streichert, Christian Haubelt, Jürgen Teich. 982-985 [doi]
- Comparing high-level modeling approaches for embedded system designLisane B. de Brisolara, Leandro Buss Becker, Luigi Carro, Flávio Rech Wagner, Carlos Eduardo Pereira, Ricardo Reis. 986-989 [doi]
- Deriving a new efficient algorithm for min-period retimingHai Zhou. 990-993 [doi]
- K-disjointness paradigm with application to symmetry detection for incompletely specified functionsKuo-Hua Wang, Jia-Hung Chen. 994-997 [doi]
- Logic optimization using rule-based randomized searchPetra Färm, Elena Dubrova, Andreas Kuehlmann. 998-1001 [doi]
- Fast synthesis of exact minimal reversible circuits using group theoryGuowu Yang, Xiaoyu Song, William N. N. Hung, Marek A. Perkowski. 1002-1005 [doi]
- Design and design automation of rectification logic for engineering changeCheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone. 1006-1009 [doi]
- Power minimization for dynamic PLAsTzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh. 1010-1013 [doi]
- Integrated algorithmic logical and physical design of integer multiplierShuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng. 1014-1017 [doi]
- Arrival time aware scheduling to minimize clock cycle lengthRafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida. 1018-1021 [doi]
- Efficient synthesis of speed-independent combinational logic circuitsW. B. Toms, David A. Edwards. 1022-1026 [doi]
- A practical cut-based physical retiming algorithm for field programmable gate arraysPeter Suaris, Dongsheng Wang, Nan-Chi Chou. 1027-1030 [doi]
- BDD-based two variable sharing extractionDennis Wu, Jianwen Zhu. 1031-1034 [doi]
- Supporting sequential assumptions in hybrid verificationEduard Cerny, Ashvin Dsouza, Kevin Harer, Pei-Hsin Ho, Hi-Keung Tony Ma. 1035-1038 [doi]
- Automatic functional test program generation for microprocessor verificationTun Li, Dan Zhu, Lei Liang, Yang Guo, Sikun Li. 1039-1042 [doi]
- Forward symbolic model checking for real time systemsGeorgios Logothetis. 1043-1046 [doi]
- Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practiceYinlei Yu, Sharad Malik. 1047-1051 [doi]
- Priority directed test generation for functional verification using neural networksHao Shen, Yuzhuo Fu. 1052-1055 [doi]
- Comparison of schemes for encoding unobservability in translation to SATMiroslav N. Velev. 1056-1059 [doi]
- Implication of assertion graphs in GSTEGuowu Yang, Jin Yang, William N. N. Hung, Xiaoyu Song. 1060-1063 [doi]
- XTW, a parallel and distributed logic simulatorQing Xu, Carl Tropper. 1064-1069 [doi]
- Comprehensive frequency dependent interconnect extraction and evaluation methodologyRong Jiang, Charlie Chung-Ping Chen. 1070-1073 [doi]
- On-chip thermal gradient analysis and temperature flattening for SoC designTakashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto. 1074-1077 [doi]
- Return path selection for loop RL extractionAkira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera. 1078-1081 [doi]
- Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnectsNatalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis. 1082-1085 [doi]
- Vector extraction for average total power estimationYongjun Xu, Jinghua Chen, Zuying Luo, Xiaowei Li. 1086-1089 [doi]
- Relaxed hierarchical power/ground grid analysisYici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu. 1090-1093 [doi]
- Sleep transistor sizing using timing criticality and temporal currentsAnand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan. 1094-1097 [doi]
- Timing analysis considering temporal supply voltage fluctuationMasanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera. 1098-1101 [doi]
- Fast, accurate MOS table model for circuit simulation using an unstructured grid and preserving monotonicityG. Peter Fang, David C. Yeh, David T. Zweidinger, Lawrence A. Arledge Jr., Vinod Gupta. 1102-1106 [doi]
- Congestion prediction in floorplanningChiu-Wing Sham, Evangeline F. Y. Young. 1107-1110 [doi]
- CMP aware shuttle mask floorplanningGang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong. 1111-1114 [doi]
- An improved P-admissible floorplan representation based on Corner Block ListRenshen Wang, Sheqin Dong, Xianlong Hong. 1115-1118 [doi]
- Fast floorplanning by look-ahead enabled recursive bipartitioningJason Cong, Michail Romesis, Joseph R. Shinnerl. 1119-1122 [doi]
- LFF algorithm for heterogeneous FPGA floorplanningJun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu. 1123-1126 [doi]
- Placement for configurable dataflow architectureMongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim. 1127-1130 [doi]
- Wire congestion and thermal aware 3D global placementKarthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim. 1131-1134 [doi]
- Placement with symmetry constraints for analog layout design using TCG-SJai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang. 1135-1137 [doi]
- An LP-based methodology for improved timing-driven placementQingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal. 1139-1143 [doi]
- Placement stability metricsCharles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz. 1144-1147 [doi]
- Redundant-via enhanced maze routing for yield improvementGang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong. 1148-1151 [doi]
- Interconnect estimation without packing via ACG floorplansJia Wang, Hai Zhou. 1152-1155 [doi]
- Timing driven track routing considering coupling capacitanceDi Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra. 1156-1159 [doi]
- Multilevel full-chip gridless routing considering optical proximity correctionTai-Chen Chen, Yao-Wen Chang. 1160-1163 [doi]
- Improving the scalability of SAMBA bus architectureRuibing Lu, Aiqun Cao, Cheng-Kok Koh. 1164-1167 [doi]
- Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line samplingJeng-Liang Tsai, Charlie Chung-Ping Chen. 1168-1171 [doi]
- Register-transfer level functional scan for hierarchical designsHo Fai Ko, Qiang Xu, Nicola Nicolici. 1172-1175 [doi]
- Using fault model relaxation to diagnose real scan chain defectsYu Huang, Wu-Tung Cheng, Greg Crowell. 1176-1179 [doi]
- A retention-aware test power model for embedded SRAMBaosheng Wang, Josh Yang, Yuejian Wu, André Ivanov. 1180-1183 [doi]
- On-chip accumulated jitter measurement for phase-locked loopsChih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang. 1184-1187 [doi]
- SoC test scheduling using the B-tree based floorplanning techniqueJen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang. 1188-1191 [doi]
- Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operandsTongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu. 1192-1195 [doi]
- Efficiently generating test vectors with state pruningYing Chen, Dennis Abts, David J. Lilja. 1196-1199 [doi]
- Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAsE. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan. 1200-1203 [doi]
- Comprehensive analysis and optimization of CMOS LNA noise performanceDong Feng, Bingxue Shi. 1204-1207 [doi]
- An analog front-end IP for 13.56MHz RFID interrogatorsJunghyun Cho, Suk-Byung Chai, Chung-Gi Song, Kyung-Won Min, Shiho Kim. 1208-1211 [doi]
- A two-stage genetic algorithm method for optimization the Sigma-Delta modulatorsAli Zahabi, Omid Shoaei, Yarallah Koolivand, Parviz Jabedar-Maralani. 1212-1215 [doi]
- A novel differential VCO circuit design for USB HubGong Qian, Yuan Guo-shun. 1216-1219 [doi]
- Static power minimization in current-mode circuitsM. S. Bhat, H. S. Jamadagni. 1220-1223 [doi]
- A novel transmitter for 1000Base-T physical transceiver1224-1227 [doi]
- A novel data processing circuit in high-speed serial communicationYongjian Tang, Lenian He, Xiaolang Yan. 1228-1231 [doi]
- A monolithic CMOS L band DAB receiverZiqiang Wang, Baoyong Chi, Min Lin, Shuguang Han, Lu Liu, Jinke Yao, Zhihua Wang. 1232-1235 [doi]
- A bipolar IF amplifier/RSSI for ASK receiverYonggang Tao, Yongsheng Xu, Wei Jin, Hui Yu, Zongsheng Lai. 1236-1239 [doi]
- Evaluation of dual V::DD:: fabrics for low power FPGAsRajarshi Mukherjee, Seda Ogrenci Memik. 1240-1243 [doi]
- Design of an application-specific PLD architectureJae-Jin Lee, Gi-Yong Song. 1244-1247 [doi]
- Event-oriented computing with reconfigurable platformMitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita. 1248-1251 [doi]
- Reconfigurable adaptive FEC system with interleavingKazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto. 1252-1255 [doi]
- An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocksAdeoye Olugbon, Sami Khawam, Tughrul Arslan, Ioannis Nousias, Iain Lindsay. 1256-1259 [doi]
- Using GALS architecture to reduce the impact of long wire delay on FPGA performanceXin Jia, Ranga Vemuri. 1260-1263 [doi]
- A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encodingTiejun Li, Sikun Li, Cheng-Dong Shen. 1264-1267 [doi]
- A fast digit-serial systolic multiplier for finite field ::::GF::::(2:::::::m:::::::)Chang Hoon Kim, Soonhak Kwon, Chun-Pyo Hong. 1268-1271 [doi]
- Adaptive fuzzy control scheduling of window-constrained real-time systemsZhu Xiangbin, Shi-liang Tu. 1272-1275 [doi]
- A high performance QAM receiver for digital cable TV with integrated A/D and FEC decoderBo Shen, Junhua Tian, Zheng Li, Jianing Su, Qianling Zhang. 1276-1279 [doi]
- Partitioned bus coding for energy reductionLin Xie, Peiliang Qiu, Qinru Qiu. 1280-1283 [doi]
- An improved bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000Yanju Han, Chao Xu, Yizhen Zhang. 1284-1287 [doi]
- A generalized quadrature bandpass sampling in radio receiversYi-Ran Sun, Svante Signell. 1288-1291 [doi]
- Reducing leakage power in instruction cache using WDC for embedded processorsXin Lu, Yuzhuo Fu. 1292-1295 [doi]
- System-level architectural exploration using allocation-on-demand techniqueQiang Wu, Jinian Bian, Hongxi Xue. 1296-1298 [doi]
- A fractional delay-locked loop for on chip clock generation applicationsPooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi. 1300-1309 [doi]
- A novel O(n) parallel banker s algorithm for System-on-a-ChipJaehwan John Lee, Vincent John Mooney III. 1304-1308 [doi]
- Hardware/software co-design using hierarchical platform-based design methodZhihui Xiong, Sikun Li, Jihua Chen. 1309-1312 [doi]
- Architecture and performance comparison of a statistic-based lottery arbiter for shared bus on chipYan Zhang. 1313-1316 [doi]
- Using loop invariants to fight soft errors in data cachesSri Hari Krishna Narayanan, Seung Woo Son, Mahmut T. Kandemir, Feihui Li. 1317-1320 [doi]