Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti. A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. In Ting-Ao Tang, editor, Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005. pages 791-794, ACM Press, 2005. [doi]
Abstract is missing.