Junpei Inoue - researchr alias

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Viewing Publication 1 - 7 from 7

2005

Evaluation of on-chip transmission line interconnect using wire length distributionJunpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu. aspdac 2005: 133-138 [doi]

Wire Length Distribution Model for System LSITakanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu. ieicet, 88-A(12):3445-3452, 2005. [doi]

Wire Length Distribution Model Considering Core Utilization for System on ChipTakanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu. isvlsi 2005: 276-277 [doi]

Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution ModelHidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu. ieicet, 88-A(12):3358-3366, 2005. [doi]

Evaluation of X Architecture Using Interconnect Length DistributionHidenari Nakashima, Naohiro Takagi, Junpei Inoue, Kenichi Okada, Kazuya Masu. ieicet, 88-A(12):3437-3444, 2005. [doi]

Prediction of delay time for future LSI using on-chip transmission line interconnectsTakumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu. slip 2005: 7-12 [doi]

2004

ULSI Interconnect Length Distribution Model Considering Core UtilizationHidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu. date 2004: 1210-1217 [doi]

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