Abstract is missing.
- High-performance ULSI: the real limiter to interconnect scalingRon Ho. 3 [doi]
- Prediction of delay time for future LSI using on-chip transmission line interconnectsTakumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu. 7-12 [doi]
- Predictions of CMOS compatible on-chip optical interconnectGuoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi. 13-20 [doi]
- Package level interconnect optionsJ. Balachandran, Steven Brebels, G. Carchon, T. Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne. 21-27 [doi]
- Multilevel full-chip routing with testability and yield enhancementKatherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen. 29-36 [doi]
- Dealing with interconnect process variationsN. S. Nagaraj. 39 [doi]
- Predicting interconnect requirements in ultra-large-scale integrated control logic circuitryMary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand. 43-50 [doi]
- Prediction model for evaluation of reconfigurable interconnects in distributed shared-memory systemsWim Heirman, Joni Dambre, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan Van Campenhout. 51-58 [doi]
- Dealing with the spatio-temporal interactions among transient power, supply noise and timingDavid J. Hathaway. 61 [doi]
- A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing toolYoung-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel. 65-72 [doi]
- The impact of interstratal interconnect density on the performance of three-dimensional integrated circuitsViet H. Nguyen, Phillip Christie. 73-78 [doi]
- Interconnect and current density stress: an introduction to electromigration-aware designJens Lienig. 81-88 [doi]
- Congestion prediction in early stagesChiu-Wing Sham, Evangeline F. Y. Young. 91-98 [doi]
- Is probabilistic congestion estimation worthwhile?Jurjen Westra, Patrick Groeneveld. 99-106 [doi]