Table of Contents

• Message from the Technical Program Chair [doi]
• Symposium Committees [doi]
• Let s Think AnalogMelvin A. Breuer. 2-5 [doi]
• Analysis of a Mask-Based Nanowire DecoderEric Rachlin, John E. Savage, Benjamin Gojman. 6-13 [doi]
• Bi-Direction Synthesis for Reversible CircuitsGuowu Yang, Xiaoyu Song, William N. N. Hung, Marek A. Perkowski. 14-19 [doi]
• Boost Logic: A High Speed Energy Recovery Circuit FamilyVisvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler. 22-27 [doi]
• High Performance Array Processor for Video DecodingJ. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin. 28-33 [doi]
• High Speed Redundant Adder and Divider in Output Prediction LogicXinyu Guo, Carl Sechen. 34-41 [doi]
• Sensing Design Issues in Deep Submicron CMOS SRAMsAiyappan Natarajan, Vijay Shankar, Atul Maheshwari, Wayne Burleson. 42-45 [doi]
• Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAsMasanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama. 46-50 [doi]
• 409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOSSheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen. 52-58 [doi]
• Quasi-Exact BDD Minimization Using Relaxed Best-First SearchRüdiger Ebendt, Rolf Drechsler. 59-64 [doi]
• Two-Phase Resonant Clock DistributionJuang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler. 65-70 [doi]
• Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient DiagramsHuiying Yang, Anuradha Agarwal, Ranga Vemuri. 71-76 [doi]
• A Modified Cascaded Sigma-Delta Modulator with Improved LinearityAna Rusu, Mohammed Ismail, Hannu Tenhunen. 77-82 [doi]
• Jitter in Deep Sub-Micron InterconnectJinwook Jang, Sheng Xu, Wayne Burleson. 84-89 [doi]
• Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCsGuilin Chen, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir. 90-95 [doi]
• eWatch: Context Sensitive System Design Case StudyAsim Smailagic, Daniel P. Siewiorek, Uwe Maurer, Anthony Rowe, Karen P. Tang. 98-103 [doi]
• A Data-Driven Approach for Embedded SecurityHendra Saputra, Ozcan Ozturk, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Richard R. Brooks. 104-109 [doi]
• System Level Methodology for Programming CMP Based Multi-Threaded Network Processor ArchitecturesVijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha. 110-116 [doi]
• Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware ArchitecturesAlexander Thomas, Jürgen Becker. 118-123 [doi]
• A High Speed Reconfigurable Gate Array for Gigahertz ApplicationsJong-Ru Guo, Chao You, Michael Chu, Okan Erdogan, Russell P. Kraft, John F. McDonald. 124-129 [doi]
• Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2:::k:::Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula. 130-135 [doi]
• An Improved Dynamic Optically Reconfigurable Gate ArrayMinoru Watanabe, Fuminori Kobayashi. 136-141 [doi]
• Lemma Exchange in a Microcontroller Based Parallel SAT SolverTobias Schubert, Bernd Becker. 142-147 [doi]
• Power Analysis of Rotary ClockZhengtao Yu, Xun Liu. 150-155 [doi]
• On Reducing Peak Current and Power during TestWei Li, Sudhakar M. Reddy, Irith Pomeranz. 156-161 [doi]
• Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed ArithmeticSoumik Ghosh, Soujanya Venigalla, Magdy Bayoumi. 162-166 [doi]
• Leakage Power Driven Behavioral Synthesis of Pipelined DatapathsRanganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori. 167-172 [doi]
• High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric NormalizationJ. H. Han, Ahmet T. Erdogan, Tughrul Arslan. 173-178 [doi]
• A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage SelectionVenkataraman Mahalingam, N. Ranganathan. 180-185 [doi]
• Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital ConvertersDaniel Hostetler, Yuan Xie. 186-191 [doi]
• Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test VolumeIl-soo Lee, Jae-Hoon Jeong, Anthony P. Ambler. 194-199 [doi]
• Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial MultiplierAvijit Dutta, Terence Rodrigues, Nur A. Touba. 200-205 [doi]
• Fault Diagnosis and Fault Model AliasingIrith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy. 206-211 [doi]
• PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial CircuitsJunhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel. 212-217 [doi]
• Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier OscillatorsTian Xia, Hao Zheng, Jing Li, Ahmed Ginawi. 218-223 [doi]
• IR Drop and Ground Bounce Awareness Timing ModelMuzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong. 226-231 [doi]
• Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing ResourcesDeepak Rautela, Rajendra S. Katti. 232-237 [doi]
• Post-Placement Pin OptimiztionJurjen Westra, Patrick Groeneveld. 238-243 [doi]
• A Low Power Embedded Dataflow CoprocessorYijun Liu, Stephen B. Furber. 246-247 [doi]
• Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS CircuitsSaraju P. Mohanty, Ramakrishna Velagapudi, Valmiki Mukherjee, Hao Li. 248-249 [doi]
• Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAsRenqiu Huang, Ranga Vemuri. 250-251 [doi]
• Analysis of Incremental Communication for Multilayer Neural Networks on a Field Programmable Gate ArrayJoshua R. Dick, Kenneth B. Kent. 252-254 [doi]
• Reduction of Power and Test Time by Removing Cluster of Don t-Care from Test Data SetIl-soo Lee, Yu-Ting Lin, Anthony P. Ambler. 255-256 [doi]
• Evaluating the Data Integrity of Memory Systems by Configurable Markov ModelsMarco Ottavi, Luca Schiano, Fabrizio Lombardi, Salvatore Pontarelli, Gian-Carlo Cardarilli. 257-259 [doi]
• Synthesis of Self-Resetting Stage Logic PipelinesAbdelhalim Alsharqawi, Abdel Ejnioui. 260-262 [doi]
• Energy Efficient Architectures for the Log-MAP Decoder through Intelligent Memory UsageIndrajit Atluri, Ashwin K. Kumaraswamy. 263-265 [doi]
• RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog SynthesisKaiping Zeng, Sorin A. Huss. 266-267 [doi]
• Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data AccessesBertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin. 268-269 [doi]
• The Use of Pre-Evaluation Phase in Dynamic CMOS LogicA. Rao, Th. Haniotakis, Y. Tsiatouhas, H. Djemil. 270-271 [doi]
• Configurable Multiprocessors for High-Performance MPEG-4 Video CodingVassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez. 272-273 [doi]
• Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELsMototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi. 274-275 [doi]
• Wire Length Distribution Model Considering Core Utilization for System on ChipTakanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu. 276-277 [doi]
• 12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator with Hybrid Control SchemesYoung Uk Yim, John F. McDonald, Russell P. Kraft. 278-279 [doi]
• A Flexible and Efficient Hardware Architecture for Real-Time Face Recognition Based on EigenfaceHau T. Ngo, Rajkiran Gottumukkal, Vijayan K. Asari. 280-281 [doi]
• A High Performance Hybrid Wave-Pipelined MultiplierSuryanarayana Tatapudi, José G. Delgado-Frias. 282-283 [doi]
• Towards Integration of Quadratic Placement and Pin AssignmentJurjen Westra, Patrick Groeneveld. 284-286 [doi]
• Balancing System Level Pipelines with Stage Voltage ScalingHui Guo, Sri Parameswaran. 287-289 [doi]
• Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware AcceleratorAlexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton. 290-291 [doi]
• Design of a QCA Memory with Parallel Read/Serial WriteMarco Ottavi, Vamsi Vankamamidi, Fabrizio Lombardi, Salvatore Pontarelli, Adelio Salsano. 292-294 [doi]
• RG-SRAM: A Low Gate Leakage Memory DesignCharan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar. 295-296 [doi]
• Increasing Data TLB Resilience to Transient ErrorsFeihui Li, Mahmut T. Kandemir. 297-298 [doi]
• RITC: Repeater Insertion with Timing Target CompensationYuantao Peng, Xun Liu. 299-300 [doi]
• Design of a Real Time System for Nonlinear Enhancement of Video Streams by an Integrated Neighborhood Dependent ApproachAdam R. Livingston, Hau T. Ngo, Ming Z. Zhang, Li Tao, Vijayan K. Asari. 301-302 [doi]
• An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric KernelsMing Z. Zhang, Hau T. Ngo, Adam R. Livingston, Vijayan K. Asari. 303-304 [doi]
• A New Organization for a Perceptron-Based Branch Predictor and Its FPGA ImplementationOswaldo Cadenas, Graham M. Megson, Daniel Jones. 305-306 [doi]
• A Hierachical Method for Wiring and Congestion PredictionFei He, Xiaoyu Song, Lerong Cheng, Guowu Yang, Zhiwei Tang, Ming Gu, Jia-Guang Sun. 307-308 [doi]
• CMOS Realization of Online Testable Reversible Logic GatesD. P. Vasudevan, Parag K. Lala, James Patrick Parkerson. 309-310 [doi]
• A Scalable Parallel SoC Architecture for Network ProcessorsJörg-Christian Niemann, Mario Porrmann, Ulrich Rückert. 311-313 [doi]
• A Comparative Study on Dicing of Multiple Project WafersMeng-Chiou Wu, Rung-Bin Lin. 314-315 [doi]