Damian Dalton - researchr alias

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Viewing Publication 1 - 14 from 14

2023

Machine Learning for Data Center Optimizations: Feature Selection Using Shapley Additive exPlanation (SHAP)Yibrah Gebreyesus, Damian Dalton, Sebastian Nixon, Davide De Chiara, Marta Chinnici. fi, 15(3):88, March 2023. [doi]

2011

Searching Extended IP-XACT Components for SoC Design Based on Requirements SimilarityChristoph Trummer, Christoph Ruggenthaler, Christoph M. Kirchsteiger, Christian Steger, Reinhold Weiß, Markus Pistauer, Damian Dalton. sj, 5(1):70-79, 2011. [doi]

2010

An IP-XACT Library extended with verification information for functionality-based component selectionCh. Ruggenthaler, Christoph Trummer, Christian Steger, Reinhold Weiß, Andreas Schuhai, Markus Pistauer, Damian Dalton. ei, 127(4):109-113, 2010. [doi]

Automated simulation-based verification of power requirements for Systems-on-ChipsChristoph Trummer, Christoph M. Kirchsteiger, Christian Steger, Reinhold Weiss, Markus Pistauer, Damian Dalton. ddecs 2010: 8-11 [doi]

2005

Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware AcceleratorAlexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton. isvlsi 2005: 290-291 [doi]

Parallel Simulation with a Generic Simulation Framework Featuring Loose CouplingMario Polaschegg, Christian Steger, Damian Dalton, Abhay Vadher. icppw 2005: 251-257 [doi]

2004

A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation EnvironmentAlexander Maili, Damian Dalton, Christian Steger. patmos 2004: 799-808 [doi]

A Generic Simulation Framework for Multiprocessor ArchitecturesMario Polaschegg, Christian Steger, Damian Dalton, Abhay Vadher. fdl 2004: 345-355 [doi]

2003

APPLES: A Full Gate-Timing FPGA-Based Hardware SimulatorDamian Dalton, Vivian Bessler, Jeffrey Griffiths, Andrew McCarthy, Abhay Vadher, Rory O Kane, Rob Quigley, Declan O Connor. fpl 2003: 1162-1165 [doi]

1999

Analysis of an Associative Array Parallel Logic SimulatorDamian Dalton. icppw 1999: 308-312 [doi]

Avoiding Conventional Overheads in Parallel Logic Simulation: A New ArchitectureDamian Dalton. hipc 1999: 364-370

The Speedup Performance of an Associative Memory Based Logic SimulatorDamian Dalton. pact 1999: 207-216 [doi]

A New Timing Mechanism Architecture for Discrete Logic Event SimulationDamian Dalton. pdpta 1999: 1236-1242

A special purpose hybrid SIMD processor for logic event simulationDamian Dalton. pdp 1999: 74-83 [doi]

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