Abstract is missing.
- Reconfigurable Circuits Using Hybrid Hall Effect DevicesSteve Ferrera, Nicholas P. Carter. 1-10 [doi]
- Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D MemoryChao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Robert W. Heikaus, Okan Erdogan, Peter F. Curran, Bryan S. Goda, Kuan Zhou, John F. McDonald. 11-20 [doi]
- Implementing an OFDM Receiver on the RaPiD Reconfigurable ArchitectureCarl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu. 21-30 [doi]
- Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-SFrancisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre. 31-40 [doi]
- An Algorithm Designer s Workbench for Platform FPGA sSumit Mohanty, Viktor K. Prasanna. 41-50 [doi]
- Prototyping for the Concurrent DevelopmentLudovico de Souza, Philip Ryan, Jason Crawford, Kevin Wong, Gregory B. Zyner, Tom McDermott. 51-60 [doi]
- ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable MatrixBingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins. 61-70 [doi]
- Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar SwitchesEryk Laskowski, Marek Tudruj. 71-80 [doi]
- Arbitrating Instructions in an pmu-Coded CCMGeorgi Kuzmanov, Stamatis Vassiliadis. 81-90 [doi]
- How Secure Are FPGAs in Cryptographic Applications?Thomas J. Wollinger, Christof Paar. 91-100 [doi]
- FPGA Implementations of the RC6 Block CipherJean-Luc Beuchat. 101-110 [doi]
- Very High Speed 17 Gbps SHACAL Encryption ArchitectureMáire McLoone, John V. McCanny. 111-120 [doi]
- Track Placement: Orchestrating Routing Structures to Maximize RoutabilityKatherine Compton, Scott Hauck. 121-130 [doi]
- Quark RoutingSean T. McCulloch, James P. Cohoon. 131-140 [doi]
- Global Routing for Lookup-Table Based FPGAs Using Genetic AlgorithmsJorge Barreiros, Ernesto Costa. 141-150 [doi]
- Virtualizing Hardware with Multi-context Reconfigurable ArraysRolf Enzler, Christian Plessl, Marco Platzner. 151-160 [doi]
- A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable DeviceHideharu Amano, Akiya Jouraku, Kenichiro Anjo. 161-170 [doi]
- Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable DeviceToshiro Kitaoka, Hideharu Amano, Kenichiro Anjo. 171-180 [doi]
- Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DESGaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat. 181-193 [doi]
- Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA AlgorithmIvan Gonzalez, Sergio López-Buedo, Francisco J. Gómez, Javier Martínez. 194-203 [doi]
- An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable ComputersAllen Michalski, Kris Gaj, Tarek A. El-Ghazawi. 204-219 [doi]
- Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power ApplicationsMichael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Sánchez-Reillo. 220-229 [doi]
- Low Power Coarse-Grained Reconfigurable Instruction Set ProcessorFrancisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal. 230-239 [doi]
- Encoded-Low Swing Technique for Ultra Low Power InterconnectRohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick. 240-251 [doi]
- Building Run-Time Reconfigurable Systems from TilesGareth Lee, George Milne. 252-261 [doi]
- Exploiting Redundancy to Speedup Reconfiguration of an FPGAIrwin Kennedy. 262-271 [doi]
- Run-Time Exchange of Mechatronic Controllers Using Partial Hardware ReconfigurationKlaus Danne, Christophe Bobda, Heiko Kalte. 272-281 [doi]
- Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGAFrançois Charot, Eslam Yahya, Charles Wagner. 282-291 [doi]
- An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES AlgorithmGiacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo. 292-302 [doi]
- Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES CoreNazar A. Saqib, Francisco Rodríguez-Henríquez, Arturo Díaz-Pérez. 303-312 [doi]
- Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop TransformationsK. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz. 313-323 [doi]
- Branch Optimisation Techniques for Hardware CompilationHenry Styles, Wayne Luk. 324-333 [doi]
- A Model for Hardware Realization of Kernel LoopsJirong Liao, Weng-Fai Wong, Tulika Mitra. 334-344 [doi]
- Programmable Asynchronous Pipeline ArraysJohn Teifel, Rajit Manohar. 345-354 [doi]
- Globally Asynchronous Locally Synchronous FPGA ArchitecturesAndrew Royal, Peter Y. K. Cheung. 355-364 [doi]
- Case Study of a Functional Genomics ApplicationTom Van Court, Martin C. Herbordt, Richard J. Barton. 365-374 [doi]
- A Smith-Waterman Systolic CellChi Wai Yu, K. H. Kwong, Kin-Hong Lee, Philip Heng Wai Leong. 375-384 [doi]
- Software DeceleratorsEric Keller, Gordon J. Brebner, Philip James-Roxby. 385-395 [doi]
- A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable ComputerTheerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk. 396-405 [doi]
- Extra-dimensional Island-Style FPGAsHerman Schmit. 406-415 [doi]
- Using Multiplexers for Control and Data in D-FabrixTony Stansfield. 416-425 [doi]
- Heterogeneous Logic Block Architectures for Via-Patterned Programmable FabricsAneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit. 426-436 [doi]
- A Real-Time Visualization System for PIVToshihito Fujiwara, Kenji Fujimoto, Tsutomu Maruyama. 437-447 [doi]
- A Real-Time Stereo Vision System with FPGAYosuke Miyajima, Tsutomu Maruyama. 448-457 [doi]
- Synthesizing on a Reconfigurable Chip an Autonomous Robot Image Processing SystemJose Antonio Boluda, Fernando Pardo. 458-467 [doi]
- Reconfigurable Hardware SAT Solvers: A Survey of SystemsIouliia Skliarova, António de Brito Ferrari. 468-477 [doi]
- Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based TechniquesRainer Feldmann, Christian Haubelt, Burkhard Monien, Jürgen Teich. 478-487 [doi]
- Hardware Implementations of Real-Time Reconfigurable WSAT VariantsRoland H. C. Yap, Stella Z. Q. Wang, Martin Henz. 488-496 [doi]
- Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange RequirementsUnai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría. 497-506 [doi]
- Time and Energy Efficient Matrix Factorization Using FPGAsSeonil Choi, Viktor K. Prasanna. 507-519 [doi]
- Improving DSP Performance with a Small Amount of Field Programmable LogicJohn Oliver, Venkatesh Akella. 520-532 [doi]
- Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGAGuillermo Payá Vayá, Marcos Martínez Peiró, Francisco Ballester, Francisco Mora Campos. 533-542 [doi]
- An FPGA System for the High Speed Extraction, Normalization and Classification of Moment DescriptorsStavros Paschalakis, Peter Lee, Miroslaw Bober. 543-552 [doi]
- Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAsAbdsamad Benkrid, Khaled Benkrid, Danny Crookes. 553-564 [doi]
- A Self-reconfiguring PlatformBrandon Blodget, Philip James-Roxby, Eric Keller, Scott McMillan, Prasanna Sundararajan. 565-574 [doi]
- Heuristics for Onine Scheduling Real-Time Tasks to Partially Reconfigurable DevicesChristoph Steiger, Herbert Walder, Marco Platzner. 575-584 [doi]
- Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable SystemsJavier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, Francky Catthoor. 585-594 [doi]
- Networks on Chip as Hardware Components of an OS for Reconfigurable SystemsThéodore Marescaux, Jean-Yves Mignolet, Andrei Bartic, W. Moffat, Diederik Verkest, Serge Vernalde, Rudy Lauwereins. 595-605 [doi]
- A Reconfigurable Platform for Real-Time Embedded Video Image ProcessingN. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk. 606-615 [doi]
- Emulation-Based Analysis of Soft Errors in Deep Sub-micron CircuitsMatteo Sonza Reorda, Massimo Violante. 616-626 [doi]
- HW-Driven Emulation with Automatic Interface GenerationM. Çakir, Eike Grimpe, Wolfgang Nebel. 627-637 [doi]
- Implementation of HW im - A Real-Time Configurable Cache SimulatorShih-Lien Lu, Konrad Lai. 638-647 [doi]
- The Bank Nth Chance Replacement Policy for FPGA-Based CAMsPaul Berube, Ashley Zinyk, José Nelson Amaral, Mike MacGregor. 648-660 [doi]
- Variable Precision Multipliers for FPGA-Based Reconfigurable Computing SystemsPasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo. 661-669 [doi]
- A New Arithmetic Unit in GF(2:::m:::) for Reconfigurable Hardware ImplementationChang Hoon Kim, Soonhak Kwon, Jong Jin Kim, Chun-Pyo Hong. 670-680 [doi]
- A Dynamic Routing Algorithm for a Bio-inspired Reconfigurable CircuitYann Thoma, Eduardo Sanchez, Juan-Manuel Moreno Aróstegui, Gianluca Tempesti. 681-690 [doi]
- An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-TimeLeonel Sousa, Pedro Tomás, Francisco J. Pelayo, Antonio Martínez, Christian A. Morillas, Samuel F. Romero. 691-700 [doi]
- Power Analysis of FPGAs: How Practical is the Attack?François-Xavier Standaert, Loïc van Oldeneel tot Oldenzeel, David Samyde, Jean-Jacques Quisquater. 701-711 [doi]
- A Power-Scalable Motion Estimation Architecture for Energy Constrained ApplicationsMaurizio Martina, Andrea Molino, Federico Quaglio, Fabrizio Vacca. 712-721 [doi]
- A Novel Approach for Architectural Model Characterization. An Example through the Systolic RingPascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Didier Demigny. 722-732 [doi]
- A Generic Architecture for Integrated Smart TransducersMartin Delvai, Ulrike Eisenmann, Wilfried Elmenreich. 733-744 [doi]
- Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAsNuno Roma, Tiago Dias, Leonel Sousa. 745-754 [doi]
- A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGATomoyoshi Kobori, Tsutomu Maruyama. 755-765 [doi]
- Implementation of ReCSiP: A ReConfigurable Cell SImulation PlatformYasunori Osana, Tomonori Fukushima, Hideharu Amano. 766-775 [doi]
- On the Implementation of a Margolus Neighborhood Cellular Automata on FPGAJoaquín Cerdá, Rafael Gadea Gironés, Vicente Herrero, Angel Sebastia. 776-785 [doi]
- Fast Modular Division for Application in ECC on Reconfigurable LogicAlan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici. 786-795 [doi]
- Non-uniform Segmentation for Hardware Function EvaluationDong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung. 796-807 [doi]
- A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGABarry Lee, Neil Burgess. 808-817 [doi]
- A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital CircuitsJ. Soares Augusto, Carlos Beltrán Almeida, H. C. Campos Neto. 818-827 [doi]
- Evaluation of Testability of Path Delay Faults for User-Configured Programmable DevicesAndrzej Krasniewski. 828-838 [doi]
- Fault Simulation Using Partially Reconfigurable HardwareA. Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa. 839-848 [doi]
- Switch Level Fault EmulationSeyed Ghassem Miremadi, Ali Reza Ejlali. 849-858 [doi]
- An Extensible, System-On-Programmable-Chip, Content-Aware Internet FirewallJohn W. Lockwood, Christopher E. Neely, Christopher K. Zuver, James Moscola, Sarang Dharmapurikar, David Lim. 859-868 [doi]
- IPsec-Protected Transport of HDTV over IPPeter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins, Pawel Chodowiec, Kris Gaj. 869-879 [doi]
- Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection SystemIoannis Sourdis, Dionisios N. Pnevmatikatos. 880-889 [doi]
- Irregular Reconfigurable CAM Structures for Firewall ApplicationsT. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay. 890-899 [doi]
- Compiling for the Molen Programming ParadigmElena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis. 900-910 [doi]
- Laura: Leiden Architecture Research and Exploration ToolClaudiu Zissulescu, Todor Stefanov, Bart Kienhuis, Ed F. Deprettere. 911-920 [doi]
- Communication Costs Driven Design Space Exploration for Reconfigurable ArchitecturesLilian Bossuet, Guy Gogniat, Jean Luc Philippe. 921-933 [doi]
- From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs TransformationsLinda Kaouane, Mohamed Akil, Yves Sorel, Thierry Grandpierre. 934-943 [doi]
- Adaptive Real-Time Systems and the FPAAStuart Colsell, Reuben Edwards. 944-947 [doi]
- Challenges and Successes in Space Based Reconfigurable ComputingMark E. Dunham, Michael P. Caffrey, Paul S. Graham. 948-951 [doi]
- Adaptive Processor: A Dynamically Reconfiguration Technology for Stream ProcessingShigeyuki Takano. 952-955 [doi]
- Efficient Reconfigurable Logic Circuits for Matching Complex Network Intrusion Detection PatternsChristopher R. Clark, David E. Schimmel. 956-959 [doi]
- FPGAs for High Accuracy Clock Synchronization over Ethernet NetworksRoland Höller. 960-963 [doi]
- Project of IPv6 Router with FPGA Hardware AcceleratorJiri Novotný, Otto Fucík, David Antos. 964-967 [doi]
- A TCP/IP Based Multi-device Programming CircuitDavid V. Schuehler, Harvey Ku, John W. Lockwood. 968-971 [doi]
- Design Flow for Efficient FPGA ReconfigurationRichard H. Turner, Roger Woods. 972-975 [doi]
- High-Level Design Tools for FPGA-Based Combinatorial AcceleratorsValery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida. 976-979 [doi]
- Using System Generator to Design a Reconfigurable Video Encryption SystemDaniel Denning, Neil Harold, Malachy Devlin, James Irvine. 980-983 [doi]
- MATLAB/Simulink Based Methodology for Rapid-FPGA-PrototypingMiroslav Lícko, Jan Schier, Milan Tichý, Markus Kühl. 984-987 [doi]
- DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband ModemsJ. Marí-Roig, V. Torres, Ma José Canet, A. Pérez, T. Sansaloni, Francisco Cardells-Tormo, F. Angarita, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat. 988-991 [doi]
- FPGA Implementation of a Maze Routing AcceleratorJohn A. Nestor. 992-995 [doi]
- Model Checking Reconfigurable Processor Configurations for Safety PropertiesJohn Cochran, Deepak Kapur, Darko Stefanovic. 996-999 [doi]
- A Statistical Analysis Tool for FPLD ArchitecturesRenqiu Huang, Tommy Cheung, Ted Kok. 1000-1003 [doi]
- FPGA-Implementation of Signal Processing Algorithms for Video Based Industrial Safety ApplicationsJörg Velten, Anton Kummert. 1004-1007 [doi]
- Configurable Hardware Architecture for Real-Time Window-Based Image ProcessingCesar Torres-Huitzil, Miguel Arias-Estrada. 1008-1011 [doi]
- An FPGA-Based Image Connected Component LabellerKhaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid. 1012-1015 [doi]
- FPGA Implementation of Adaptive Non-linear Predictors for Video CompressionRafael Gadea Gironés, Agustín Ramirez-Agundis, Joaquín Cerdá-Boluda, Ricardo José Colom-Palero. 1016-1019 [doi]
- Reconfigurable Systems in EducationValery Sklyarov, Iouliia Skliarova. 1020-1023 [doi]
- Data Dependent Circuit Design: A Case StudyShoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto. 1024-1027 [doi]
- Design of a Power Conscious, Customizable CDMA ReceiverMaurizio Martina, Andrea Molino, Mario Nicola, Fabrizio Vacca. 1028-1031 [doi]
- Power-Efficient Implementations of Multimedia Applications on Reconfigurable PlatformsKonstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis. 1032-1035 [doi]
- A VHDL Library to Analyse Fault Tolerant TechniquesPilar Martínez Ortigosa, O. López, R. Estrada, Inmaculada García, Ester M. Garzón. 1036-1039 [doi]
- Hardware Design with a Scripting LanguagePer Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai. 1040-1043 [doi]
- Testable Clock Routing Architecture for Field Programmable Gate ArraysL. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti. 1044-1047 [doi]
- FPGA Implemenation of Multi-layer Perceptrons for Speech RecognitionEva M. Ortigosa, Pilar Martínez Ortigosa, Antonio Cañas, Eduardo Ros, Rodrigo Agís, Julio Ortega. 1048-1052 [doi]
- FPGA Based High Density Spiking Neural Network ArrayJuan M. Xicotencatl, Miguel Arias-Estrada. 1053-1056 [doi]
- FPGA-Based Computation of Free-Form DeformationsJun Jiang, Wayne Luk, Daniel Rueckert. 1057-1061 [doi]
- FPGA Implementations of Neural Networks - A Survey of a Decade of ProgressJihan Zhu, Peter Sutton. 1062-1066 [doi]
- FPGA-Based Hardware/Software CoDesign of an Expert System ShellAurel Netin, Dumitru Roman, Octavian Cret, Kalman Pusztai, Lucia Vacariu. 1067-1070 [doi]
- Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer SystemTheerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk. 1071-1074 [doi]
- Hardware-Software Codesign in Embedded Asymmetric Cryptographiy Application - A Case StudyMartin Simka, Viktor Fischer, Milos Drutarovský. 1075-1078 [doi]
- On-chip and Off-chip Real-Time Debugging for Remotely-Accessed Embedded Programmable SystemsJim Harkin, Michael Callaghan, Chris Peters, T. Martin McGinnity, Liam P. Maguire. 1079-1082 [doi]
- Fast Region Labeling on the Reconfigurable Platform ACE-VChristian Schmidt, Andreas Koch. 1083-1086 [doi]
- Modified Fuzzy C-Means Clustering Algorithm for Real-Time ApplicationsJesús Lázaro, Jagoba Arias, José Luis Martín, Carlos Cuadrado. 1087-1090 [doi]
- Reconfigurable Hybrid Architecture for Web ApplicationsDavid Rodríguez Lozano, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido. 1091-1094 [doi]
- FPGA Implementation of the Adpaptive Lattice FilterAntonin Hermanek, Zdenek Pohl, Jiri Kadlec. 1095-1098 [doi]
- Specifying Control Logic for DSP Applications in FPGAJonathan Ballagh, James Hwang, H. Ma, Brent Milne, Nabeel Shirazi, Vinay Singh, Jeffrey D. Stroomer. 1099-1102 [doi]
- FPGA Processor for Real-Time Optical Flow ComputationSelene Maya-Rueda, Miguel Arias-Estrada. 1103-1106 [doi]
- A Data Acquisition Reconfigurable Coprocessor for Virtual Instrumentation ApplicationsMaría Dolores Valdés, María José Moure, Camilo Quintáns, Enrique Mandado. 1107-1110 [doi]
- Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable ArchitecturesTudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek. 1111-1114 [doi]
- A Controlled Data-Path Allocation Model for Dynamic Run-Time Reconfiguration of FPGA DevicesDylan Carline, Paul Coulton. 1115-1118 [doi]
- Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable PlatformsSergej Sawitzki, Rainer G. Spallek. 1119-1122 [doi]
- Efficient Implementation of the Singular Value Decomposition on a Reconfigurable SystemChristophe Bobda, Klaus Danne, André Linarth. 1123-1126 [doi]
- A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2:::m:::)José Luis Imaña, Juan Manuel Sánchez. 1127-1130 [doi]
- A Study on the Design of Floating-Point Functions in FPGAsFernando E. Ortiz, John R. Humphrey, James P. Durbano, Dennis W. Prather. 1131-1134 [doi]
- Design and Implementation of RNS-Based Adaptive FiltersJavier Ramírez, Uwe Meyer-Bäse, Antonio García, Antonio Lloris-Ruíz. 1135-1138 [doi]
- Domain-Specific Reconfigurable Array for Distributed ArithmeticSami Khawam, Tughrul Arslan, Fred Westall. 1139-1144 [doi]
- Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model CheckingTomoya Kitani, Yoshifumi Takamoto, Isao Naka, Keiichi Yasumoto, Akio Nakata, Teruo Higashino. 1145-1148 [doi]
- Custom Tag Computation Circuit for a 10Gbps SCFQ SchedulerBrendan McAllister, Sakir Sezer, Ciaran Toal. 1149-1152 [doi]
- Exploiting Stateful Inspection of Network Security in Reconfigurable HardwareShaomeng Li, Jim Torresen, Oddvar Søråsen. 1153-1157 [doi]
- Propose of a Hardware Implementation for Fingerprint SystemsVanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes. 1158-1161 [doi]
- APPLES: A Full Gate-Timing FPGA-Based Hardware SimulatorDamian Dalton, Vivian Bessler, Jeffrey Griffiths, Andrew McCarthy, Abhay Vadher, Rory O Kane, Rob Quigley, Declan O Connor. 1162-1165 [doi]
- Designing, Scheduling, and Allocating Flexible Arithmetic ComponentsVinu Vijay Kumar, John Lach. 1166-1169 [doi]
- UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware DebuggingMiguel Angel Aguirre Echánove, Jonathan Noel Tombs, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo. 1170-1173 [doi]