Akio Nakata - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 22 from 22

2018

An Improved LLF Scheduling for Reducing Maximum Heap Memory Consumption by Considering Laxity TimeYuki Machigashira, Akio Nakata. tase 2018: 144-149 [doi]

2006

A Timed Failure Equivalence Preserving Abstraction for Parametric Time-interval AutomataAkio Nakata, Tadaaki Tanimoto, Suguru Sasaki, Teruo Higashino. ijfcs, 17(4):833-850, 2006. [doi]

A real time budgeting method for module-level-pipelined bus based system using bus scenariosTadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Teruo Higashino. dac 2006: 37-42 [doi]

2005

Double Depth First Search Based Parametric Analysis for Parametric Time-Interval AutomataTadaaki Tanimoto, Akio Nakata, Hideaki Hashimoto, Teruo Higashino. ieicet, 88-A(11):3007-3021, 2005. [doi]

Automatic Decomposition of Java Program for Implementation on Mobile TerminalsTakaaki Umedu, Shigeharu Urata, Akio Nakata, Teruo Higashino. aina 2005: 544-549 [doi]

2004

2003

Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model CheckingTomoya Kitani, Yoshifumi Takamoto, Isao Naka, Keiichi Yasumoto, Akio Nakata, Teruo Higashino. fpl 2003: 1145-1148 [doi]

A test sequence generation method for communication protocols using the SAT algorithmTakanori Mori, Hirotaka Otsuka, Nobuo Funabiki, Akio Nakata, Teruo Higashino. scjapan, 34(11):20-29, 2003. [doi]

2002

2001

A Conformance Testing Method for Communication Protocols Modeled as Concurrent DFSMsAtsushi Fukada, Akio Nakata, Junji Kitamichi, Teruo Higashino, Ana R. Cavalli. icoin 2001: 155-162 [doi]

Deriving Parameter Conditions for Periodic Timed Automata Satisfying Real-Time Temporal Logic FormulasAkio Nakata, Teruo Higashino. forte 2001: 151-168

1999

Generating Test Cases for a Timed I/O Automaton ModelTeruo Higashino, Akio Nakata, Kenichi Taniguchi, Ana R. Cavalli. pts 1999: 197-214

1998

Protocol Synthesis from Context-Free Processes Using Event StructuresAkio Nakata, Teruo Higashino, Kenichi Taniguchi. rtcsa 1998: 173-180 [doi]

1996

Time-Action Alternating Model for Timed LOTOS and its Symbolic Verification of Bisimulation EquivalenceAkio Nakata, Teruo Higashino, Kenichi Taniguchi. forte 1996: 279-294

1995

Verification of Liveness Property for Communicating FSM s with Conditional Transitions Depending on State Visiting NumbersTeruo Higashino, Akio Nakata, Tatsuo Itoh, Kenichi Taniguchi. forte 1996: 433-440

Protocol synthesis from timed and structured specificationsAkio Nakata, Teruo Higashino, Kenichi Taniguchi. icnp 1995: 74 [doi]

1993

LOTOS enhancement to specify time constraint among non-adjacent actions using first order logicAkio Nakata, Teruo Higashino, Kenichi Taniguchi. forte 1994: 451-466

Sign in or sign up to see more results.

runs on WebDSL