Abstract is missing.
- The Age of Adaptive Computing Is HerePaul Master. 1-3 [doi]
- Disruptive Trends by Data-Stream-Based ComputingReiner W. Hartenstein. 4 [doi]
- Multithreading for Logic-Centric SystemsGordon J. Brebner. 5-14 [doi]
- Fast Prototyping with Co-operation of Simulation and EmulationSiavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali. 15-25 [doi]
- How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping ProjectHelena Krupnova, Veronique Meurou, Christophe Barnichon, Carlos Serra, Farid Morsi. 26-35 [doi]
- Implementing Asynchronous Circuits on LUT Based FPGAsQuoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland. 36-46 [doi]
- A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and TransformationsBeniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo. 47-58 [doi]
- Flexible Routing Architecture Generation for Domain-Specific Reconfigurable SubsystemsKatherine Compton, Akshay Sharma, Shawn Phillips, Scott Hauck. 59-68 [doi]
- iPACE-V1: A Portable Adaptive Computing Engine for Real Time ApplicationsJawad Khan, Manish Handa, Ranga Vemuri. 69-78 [doi]
- Field-Programmable Custom Computing Machines - A Taxonomy -Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers. 79-88 [doi]
- Embedded Reconfigurable Logic Core for DSP ApplicationsKatarzyna Leijten-Nowak, Jef L. van Meerbergen. 89-101 [doi]
- Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB StandardFrancisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre, Vicente Torres-Carot. 102-111 [doi]
- FPGA QAM Demodulator DesignChris Dick, Fred Harris. 112-121 [doi]
- Analytical Framework for Switch Block DesignGuy G. Lemieux, David M. Lewis. 122-131 [doi]
- Modular, Fabric-Specific Synthesis for Programmable ArchitecturesAneesh Koorapaty, Lawrence T. Pileggi. 132-141 [doi]
- On Optimum Designs of Universal Switch BlocksHongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung. 142-151 [doi]
- Improved Functional Simulation of Dynamically Reconfigurable LogicIan Robertson, James Irvine, Patrick Lysaght, David Robinson. 152-161 [doi]
- Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits TechnologySergio López-Buedo, Paula Riviere, Pablo Pernas, Eduardo I. Boemo. 162-170 [doi]
- Dynamic Reconfiguration in Mobile SystemsGerard J. M. Smit, Paul J. M. Havinga, Lodewijk T. Smit, Paul M. Heysters, Michèl A. J. Rosien. 171-181 [doi]
- Using PARBIT to Implement Partial Run-Time Reconfigurable SystemsEdson L. Horta, John W. Lockwood, Sergio Takeo Kofuji. 182-191 [doi]
- Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAsRichard H. Turner, Roger Woods, Tim Courtney. 192-201 [doi]
- Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov ModelsStephen J. Melnikoff, Steven F. Quigley, Martin J. Russell. 202-211 [doi]
- FPGA Implementation of the Wavelet Packet Transform for High Speed CommunicationsAntony Jamin, Petri Mähönen. 212-221 [doi]
- A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits:::TM:::A. Carreira, T. W. Fox, L. E. Turner. 222-231 [doi]
- Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic DevicesValavan Manohararajah, Terry Borer, Stephen Dean Brown, Zvonko G. Vranesic. 232-241 [doi]
- Rapid and Reliable Routability Estimation for FPGAsPariVallal Kannan, Shankar Balachandran, Dinesh Bhatia. 242-252 [doi]
- Integrated Iterative Approach to FPGA PlacementMartin Danek, Zdenek Muzikár. 253-262 [doi]
- TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAsLucídio dos Anjos Formiga Cabral, Júlio S. Aude, Nelson Maculan. 263-270 [doi]
- High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable DevicesRafal Kielbik, Juan Manuel Moreno, Andrzej Napieralski, Grzegorz Jablonski, Tomasz Szymanski. 271-280 [doi]
- High Speed Homology Search Using Run-Time ReconfigurationYoshiki Yamaguchi, Yosuke Miyajima, Tsutomu Maruyama, Akihiko Konagaya. 281-291 [doi]
- Partially Reconfigurable Cores for Xilinx VirtexMatthias Dyer, Christian Plessl, Marco Platzner. 292-301 [doi]
- On-line Defragmentation for Run-Time Partially Reconfigurable FPGAsManuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. M. Ferreira. 302-311 [doi]
- A Flexible Power Model for FPGAsKara K. W. Poon, Andy Yan, Steven J. E. Wilton. 312-321 [doi]
- A Clocking Technique with Power Savings in Virtex-Based Pipelined DesignsOswaldo Cadenas, Graham M. Megson. 322-331 [doi]
- Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless SensorMaurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni. 332-339 [doi]
- A Tool for Activity Estimation in FPGAsElias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo. 340-349 [doi]
- FSM Decomposition for Low Power in FPGAGustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo. 350-359 [doi]
- Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric SearchGi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar. 360-369 [doi]
- A Prolog-Based Hardware Development EnvironmentKhaled Benkrid, Danny Crookes, Abdsamad Benkrid, S. Belkacemi. 370-380 [doi]
- Fly - A Modifiable Hardware CompilerChun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner. 381-390 [doi]
- Challenges and Opportunities for FPGA PlatformsIvo Bolsens. 391-392 [doi]
- Design and Implementation of FPGA Circuits for High Speed Network MonitorsMasayuki Kirimura, Yoshifumi Takamoto, Takanori Mori, Keiichi Yasumoto, Akio Nakata, Teruo Higashino. 393-403 [doi]
- Granidt: Towards Gigabit Rate Network Intrusion Detection TechnologyMaya Gokhale, Dave Dubois, Andy Dubois, Mike Boorman, Steve Poole, Vic Hogsett. 404-413 [doi]
- Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving TechniquesChannakeshav, Kuan Zhou, Jong-Ru Guo, Chao You, Bryan S. Goda, Russell P. Kraft, John F. McDonald. 414-423 [doi]
- Field-Programmable Analog Arrays: A Floating-Gate ApproachTyson S. Hall, Paul E. Hasler, David V. Anderson. 424-433 [doi]
- A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the ModelKazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida. 434-443 [doi]
- A Framework for Teaching (Re)Configurable Architectures in Student ProjectsThilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner. 444-451 [doi]
- Specialized Hardware for Deep Network Packet FilteringYoung H. Cho, Shiva Navab, William H. Mangione-Smith. 452-461 [doi]
- Implementation of a Successive Erasure BCH(16, 7, 6) Decoder and Performance Simulation by Rapid PrototypingThomas Buerner. 462-471 [doi]
- U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and ImplementationJavier Ramírez, Antonio García. 472-481 [doi]
- UltraSONIC: A Reconfigurable Architecture for Video Image ProcessingSimon D. Haynes, Henry G. Epsom, Richard J. Cooper, Paul L. McAlpine. 482-491 [doi]
- Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGATrevor W. Fox, Laurence E. Turner. 492-502 [doi]
- Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGAAlexander Staller, Peter Dillinger, Reinhard Männer. 503-512 [doi]
- Small Multiplier-Based Multiplication and Division Operators for Virtex-II DevicesJean-Luc Beuchat, Arnaud Tisserand. 513-522 [doi]
- Automating Customisation of Floating-Point DesignsAltaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang. 523-533 [doi]
- Energy-Efficient Matrix Multiplication on FPGAsJu-wook Jang, Seonil Choi, Viktor K. Prasanna. 534-544 [doi]
- Run-Time Adaptive Flexible Instruction ProcessorsShay Ping Seng, Wayne Luk, Peter Y. K. Cheung. 545-555 [doi]
- DARP - A Digital Audio Reconfigurable ProcessorJosé T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura. 556-566 [doi]
- System-Level Modelling for Performance Estimation of Reconfigurable CoprocessorsStephen Charlwood, Jonathan Mangnall, Steven F. Quigley. 567-576 [doi]
- An FPGA Based SHA-256 ProcessorKurt K. Ting, Steve C. L. Yuen, Kin-Hong Lee, Philip Heng Wai Leong. 577-585 [doi]
- Handling FPGA Faults and Configuration Sequencing Using a Hardware ExtensionPeter Zipf, Manfred Glesner, Christine Bauer, Hans Wojtkowiak. 586-595 [doi]
- On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAsAndrzej Krasniewski. 596-606 [doi]
- Simulation-Based Analysis of SEU Effects on SRAM-based FPGAsMaurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 607-615 [doi]
- Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAsAndrzej Krasniewski. 616-626 [doi]
- Logarithmic Number System and Floating-Point Arithmetics on FPGARudolf Matousek, Milan Tichý, Zdenek Pohl, Jiri Kadlec, Christopher I. Softley, Nick Coleman. 627-636 [doi]
- Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA ArchitectureEric Roesler, Brent E. Nelson. 637-646 [doi]
- Morphable MultipliersSilviu M. S. A. Chiricescu, Michael A. Schuette, Robin Glinton, Herman Schmit. 647-656 [doi]
- A Library of Parameterized Floating-Point Modules and Their UsePavle Belanovic, Miriam Leeser. 657-666 [doi]
- Wordlength as an Architectural Parameter for Reconfigurable Computing DevicesTony Stansfield. 667-676 [doi]
- An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC PlatformsMassimo Baleani, Massimo Conti, Alberto Ferrari, Valerio Frascolla, Alberto L. Sangiovanni-Vincentelli. 677-686 [doi]
- Introducing ReConfigME: An Operating System for Reconfigurable ComputingGrant B. Wigley, David A. Kearney, David Warren. 687-697 [doi]
- Efficient Metacomputation Using Self-ReconfigurationReetinder P. S. Sidhu, Viktor K. Prasanna. 698-709 [doi]
- An FPGA Co-processor for Real-Time Visual TrackingMiguel Arias-Estrada, Eduardo Rodríguez-Palacios. 710-719 [doi]
- Implementation of 3-D Adaptive LUM Smoother in Reconfigurable HardwareViktor Fischer, Milos Drutarovský, Rastislav Lukac. 720-729 [doi]
- Custom Coprocessor Based Matrix Algorithms for Image and Signal ProcessingAbbes Amira, Ahmed Bouridane, Peter Milligan, Faycal Bensaali. 730-739 [doi]
- Parallel FPGA Implementation of the Split and Merge Discrete Wavelet TransformNazeeh Aranki, Alexander Moopenn, Raoul Tawel. 740-749 [doi]
- Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2)Tim Kerins, Emanuel M. Popovici, William P. Marnane, Patrick Fitzpatrick. 750-759 [doi]
- 8 Gigabits per Second Implementation of the IDEA Cryptographic AlgorithmAntti Hämäläinen, Matti Tommiska, Jorma Skyttä. 760-769 [doi]
- Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable PlatformEmmanuel A. Moreira, Paul L. McAlpine, Simon D. Haynes. 770-779 [doi]
- A Cryptanalytic Time-Memory Tradeoff: First FPGA ImplementationJean-Jacques Quisquater, François-Xavier Standaert, Gaël Rouvroy, Jean-Pierre David, Jean-Didier Legat. 780-789 [doi]
- Creating a World of Smart Re-configurable DevicesRudy Lauwereins. 790-794 [doi]
- Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAsThéodore Marescaux, Andrei Bartic, Diederik Verkest, Serge Vernalde, Rudy Lauwereins. 795-805 [doi]
- Multitasking Hardware on the SLAAC1-V Reconfigurable Computing SystemWesley J. Landaker, Michael J. Wirthlin, Brad L. Hutchings. 806-815 [doi]
- The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived PerformanceTuomas Valtonen, Jouni Isoaho, Hannu Tenhunen. 816-825 [doi]
- An FPGA Implementation of a Multi-comparand Multi-search Associative ProcessorZbigniew Kokosinski, Wojciech Sikora. 826-835 [doi]
- AES Implementation on FPGA: Time - Flexibility TradeoffAnna Labbé, Annie Pérez. 836-844 [doi]
- An FPGA Implementation of the Linear CryptanalysisFrançois Koeune, Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David, Jean-Didier Legat. 845-852 [doi]
- Compiling Application-Specific HardwareMihai Budiu, Seth Copen Goldstein. 853-863 [doi]
- XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP ArchitectureJoão M. P. Cardoso, Markus Weinhardt. 864-874 [doi]
- Sea Cucumber: A Synthesizing Compiler for FPGAsJustin L. Tripp, Preston A. Jackson, Brad L. Hutchings. 875-885 [doi]
- Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAsJoan Carletta, M. D. Rayman. 886-896 [doi]
- Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDsUwe Meyer-Bäse, Javier Ramírez, Antonio García. 897-904 [doi]
- High Performance Quadrature Digital Mixers for FPGAsFrancisco Cardells-Tormo, Javier Valls-Coquillat. 905-914 [doi]
- HAGAR: Efficient Multi-context Graph ProcessorsOskar Mencer, Zhining Huang, Lorenz Huelsbergen. 915-924 [doi]
- Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing PlatformBenjamin Carrión Schäfer, Steven F. Quigley, Andrew H. C. Chan. 925-934 [doi]
- On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP ApproachKai-Pui Lam, Sui-Tung Mak. 935-944 [doi]
- REFLIX: A Processor Core for Reactive Embedded ApplicationsZoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli. 945-945 [doi]
- Factors Influencing the Performance of a CPU-RFU Hybrid ArchitectureGirish Venkataramani, Suraj Sudhir, Mihai Budiu, Seth Copen Goldstein. 955-965 [doi]
- Implementing Converters in FPLDAlfredo Sanz, José I. García-Nicolás, Isidoro Urriza. 966-975 [doi]
- A Quantitative Understanding of the Performance of Reconfigurable CoprocessorsDomingo Benitez. 976-986 [doi]
- Integration of Reconfigurable Hardware into System-Level DesignKlaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier. 987-996 [doi]
- A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable ArchitecturesFrank Wolz, Reiner Kolla. 997-1006 [doi]
- The Integration of SystemC and Hardware-Assisted VerificationRamaswamy Ramaswamy, Russell Tessier. 1007-1016 [doi]
- Using Design Hierarchy to Improve Quality of Results in FPGAsAlireza Kaviani. 1017-1026 [doi]
- Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain ImplementationsGeorge Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis. 1027-1036 [doi]
- A General Hardware Design Model for Multicontext FPGAsNaoto Kaneko, Hideharu Amano. 1037-1047 [doi]
- Dynamically Reconfigurable Hardware - A New Perspective for Neural Network ImplementationsMario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert. 1048-1057 [doi]
- A Compilation Framework for a Dynamically Reconfigurable ArchitectureRaphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys. 1058-1067 [doi]
- Data Dependent Circuit for Subgraph Isomorphism ProblemShuichi Ichikawa, Shoji Yamamoto. 1068-1071 [doi]
- Exploration of Design Space in ECDSAJan Schmidt, Martin Novotný, Martin Jäger, Milos Becvár, Michal Jáchim. 1072-1075 [doi]
- 2D and 3D Computer Graphics Algorithms under MORPHOSYSIssam Damaj, Sohaib Majzoub, Hassan B. Diab. 1076-1079 [doi]
- A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-ChipSpyros Blionas, Kostas Masselos, Chrissavgi Dre, Christos Drosos, F. Z. Ieromnimon, T. Pagonis, A. Pneymatikakis, Anna Tatsaki, T. Trimis, A. Vontzalidis, Dimitris Metafas. 1080-1083 [doi]
- SoftTOTEM: An FPGA Implementation of the TOTEM Parallel ProcessorStephanie McBader, Luca Clementel, Alvise Sartori, Andrea Boni, Peter Lee. 1084-1087 [doi]
- Real-Time Medical Diagnosis on a Multiple FPGA-based SystemTakashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba. 1088-1091 [doi]
- Threshold Element-Based Symmetric Function Generators and Their Functional ExtensionKazuo Aoyama, Hiroshi Sawada. 1092-1096 [doi]
- Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural NetworksWolfgang Schlecker, Achim Engelhart, Werner G. Teich, Hans-Jörg Pfleiderer. 1097-1100 [doi]
- Building Custom FIR Filters Using System GeneratorJames Hwang, Jonathan Ballagh. 1101-1104 [doi]
- SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network ApplicationsKlaus Feske, Georg Heinrich, Berndt Fritzsche, Mark Langer. 1105-1109 [doi]
- Dynamic Constant Coefficient Convolvers Implemented in FPGAsErnest Jamro, Kazimierz Wiatr. 1110-1113 [doi]
- VIZARD II: An FPGA-based Interactive Volume Rendering SystemUrs Kanus, Gregor Wetekam, Johannes Hirche, Michael Meißner. 1114-1117 [doi]
- RHiNET/NI: A Reconfigurable Network Interface for Cluster ComputingNaoyuki Izu, Tomonori Yokoyama, Junichiro Tsuchiya, Konosuke Watanabe, Hideharu Amano. 1118-1121 [doi]
- General Purpose Prototyping Platform for Data-Processor Research and DevelopmentFilip Miletic, Rene van Leuken, Alexander de Graaf. 1122-1125 [doi]
- High Speed Computation of Three Dimensional Cellular Automata with FPGATomoyoshi Kobori, Tsutomu Maruyama. 1126-1130 [doi]
- SOPC-based Embedded Smart Strain Gage SensorSylvain Poussier, Hassan Rabah, Serge Weber. 1131-1134 [doi]
- Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific ApplicationsYajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man. 1135-1138 [doi]
- An FPGA-based Node Controller for a High Capacity WDM Optical Packet NetworkRoberto Gaudino, Vito De Feo, Marcello Chiaberge, Claudio Sansoè. 1139-1143 [doi]
- FPGA and Mixed FPGA-DSP Implementations of Electrical Drive AlgorithmsFrancis Calmon, M. Fathallah, P. J. Viverge, Christian Gontrand, Jordi Carrabina, P. Foussier. 1144-1147 [doi]
- Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable ComputerWim J. C. Melis, Peter Y. K. Cheung, Wayne Luk. 1148-1151 [doi]
- A Novel Watermarking Technique for LUT Based FPGA DesignsDylan Carline, Paul Coulton. 1152-1155 [doi]
- Implementing CSAT Local Search on FPGAsMartin Henz, Edgar Tan, Roland H. C. Yap. 1156-1159 [doi]
- A Reconfigurable Processor ArchitectureAdronis Niyonkuru, Göran Eggers, Hans Christoph Zeidler. 1160-1163 [doi]
- A Reconfigurable System-on-Chip-Based Fast EDM Process MonitorSebastian Friebe, Steffen Köhler, Rainer G. Spallek, Henrik Juhr, Klaus Künanz. 1164-1167 [doi]
- Gene Matching Using JBitsSteve Guccione, Eric Keller. 1168-1171 [doi]
- Massively Parallel/Reconfigurable Emulation Model for the D-algorithmDaniel G. Saab, Fatih Kocan, Jacob A. Abraham. 1172-1176 [doi]
- A Placement/Routing Approach for FPGA AcceleratorsAkira Miyashita, Toshihito Fujiwara, Tsutomu Maruyama. 1177-1182 [doi]