Laurence E. Turner - researchr alias

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Viewing Publication 1 - 17 from 17

2006

Bit-Serial Digital Filter Implementation using a Custom C CompilerDan Cyca, Laurence E. Turner. apccas 2006: 534-537 [doi]

A C compiler for implementing FPGA based bit-serial DSP systemsDan Cyca, Laurence E. Turner. fpt 2006: 305-308 [doi]

2004

Graphics processor unit (GPU) acceleration of finite-difference time-domain (FDTD) algorithmSean E. Krakiwsky, Laurence E. Turner, Michal M. Okoniewski. iscas 2004: 265-268

A Field Programmable Bit-Serial Digital Signal ProcessorS. A. Rahim, Laurence E. Turner. iwsoc 2004: 295-298 [doi]

2003

A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAsAlex Carreira, Trevor W. Fox, Laurence E. Turner. ejasp, 2003(6):555-564, 2003. [doi]

Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform ApproximationsTrevor W. Fox, Laurence E. Turner. ejasp, 2003(6):543-554, 2003. [doi]

2002

1997

An FPGA implementation of a matched filter detector for spread spectrum communications systemsT. Mathews, S. G. Gibb, Laurence E. Turner, Peter J. W. Graumann, M. Fattouche. fpl 1997: 364-373

1995

Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAsG. Panneerselvam, Peter J. W. Graumann, Laurence E. Turner. fpl 1995: 272-281

Rapid Hardware Prototyping of Digital Signal Processing Systems Using FPGAsLaurence E. Turner, Peter J. W. Graumann. fpl 1995: 129-138

BIT-Serial FIR Filters with CSD Coefficients for FPGAsLaurence E. Turner, Peter J. W. Graumann, S. G. Gibb. fpl 1995: 311-320

1994

DSP System Synthesis Including Variable Data Path WidthBruce A. Johnston, Peter J. W. Graumann, Laurence E. Turner. iscas 1994: 53-56

1991

Pipelined BIT-Serial SYNthesis of Digital Filerting AlgorithmsR. Nagalla, Laurence E. Turner. vlsi 1992: 39-48

1984

A bit serial LDI recursive digital filterLaurence E. Turner, Peter B. Denyer, David S. Renshaw. icassp 1984: 238-241 [doi]

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