K. R. Shesha Shayee - researchr alias

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Viewing Publication 1 - 3 from 3

2004

Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop TransformationsJoonseok Park, Pedro C. Diniz, K. R. Shesha Shayee. TC, 53(11):1420-1435, 2004. [doi]

2003

Performance and Area Modeling of Complete FPGA Designs in the presence of Loop TransformationsK. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz. fccm 2003: 296 [doi]

Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop TransformationsK. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz. fpl 2003: 313-323 [doi]

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