Abstract is missing.
- A High I/O Reconfigurable Crossbar SwitchSteve Young, Peter Alfke, Colm Fewer, Scott McMillan, Brandon Blodget, Delon Levi. 3-10 [doi]
- Congruential Sieves on a Reconfigurable ComputerHeather A. Wake, Duncan A. Buell. 11-18 [doi]
- Performance Analysis of Fixed, Reconfigurable, and Custom Architectures for the SCAN Image and Video Encryption AlgorithmApostolos Dollas, Christopher Kachris, Nikolaos G. Bourbakis. 19 [doi]
- Implementation of a Content-Scanning Module for an Internet FirewallJames Moscola, John W. Lockwood, Ronald Prescott Loui, Michael Pachos. 31-38 [doi]
- Compiling Policy Descriptions into Reconfigurable Firewall ProcessorsT. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay. 39 [doi]
- Compact FPGA-based True and Pseudo Random Number GeneratorsKuen Hung Tsoi, K. H. Leung, Philip Heng Wai Leong. 51-61 [doi]
- Accelerating Bit Error Rate Testing Using a System Level Design ToolVinay Singh, Ann Root, E. Hemphill, Nabeel Shirazi, James Hwang. 62-68 [doi]
- A Hardware Gaussian Noise Generator for Channel Code EvaluationDong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung. 69 [doi]
- Perturbation Analysis for Word-length OptimizationGeorge A. Constantinides. 81-90 [doi]
- Improved Small Multiplier Based Multiplication, Squaring and DivisionB. R. Lee, Neil Burgess. 91 [doi]
- Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable ExecutableBenjamin A. Levine, Herman Schmit. 101-110 [doi]
- Issues and Approaches to Coarse-Grain Reconfigurable Architecture DevelopmentKenneth Eguro, Scott Hauck. 111-120 [doi]
- Asynchronous PipeRench: Architecture and Performance EstimationsHiroto Kagotani, Herman Schmit. 121 [doi]
- The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration UpsetsMichael J. Wirthlin, Darrel Eric Johnson, Nathan Rollins, Michael Caffrey, Paul Graham. 133-142 [doi]
- Adaptive Fault Recovery for Networked Reconfigurable SystemsWeifeng Xu, Ramshankar Ramanarayanan, Russell Tessier. 143 [doi]
- Gamma-Ray Pulsar Detection using Reconfigurable Computing HardwareJanette Frigo, David Palmer, Maya Gokhale, Marc Popkin-Paine. 155-161 [doi]
- Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGAAbdsamad Benkrid, Khaled Benkrid, Danny Crookes. 162-172 [doi]
- Runtime Assignment of Reconfigurable Hardware Components for Image Processing PipelinesHeather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis. 173 [doi]
- Floating Point Unit Generation and Evaluation for FPGAsJian Liang, Russell Tessier, Oskar Mencer. 185-194 [doi]
- Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAsXiaojun Wang, Brent E. Nelson. 195 [doi]
- Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data StructuresPedro C. Diniz, Joonseok Park. 207-217 [doi]
- Simulation and Synthesis of CSP-based Interprocess CommunicationPreston A. Jackson, Brad L. Hutchings, Justin L. Tripp. 218-227 [doi]
- Source Level Debugger for the Sea Cucumber Synthesizing CompilerK. Scott Hemmert, Justin L. Tripp, Brad L. Hutchings, Preston A. Jackson. 228 [doi]
- Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of ApplicationsJingzhao Ou, Seonil Choi, Viktor K. Prasanna. 241-250 [doi]
- Reconfigurable Computing Application FrameworksAnthony L. Slade, Brent E. Nelson, Brad L. Hutchings. 251 [doi]
- Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware DesignPrithviraj Banerjee, Debabrata Bagchi, Malay Haldar, Anshuman Nayak, Victor Kim, R. Uribe. 263-264 [doi]
- Fast Reconfiguration Through Difference CompressionIrwin Kennedy. 265-266 [doi]
- FPGA-based SIMD ProcessorStanley Y. C. Li, Gap C. K. Cheuk, Kin-Hong Lee, Philip Heng Wai Leong. 267-268 [doi]
- Implementation of Three-Dimensional FPGA-Based FDTD Solvers: An Architectural OverviewJames P. Durbano, Fernando E. Ortiz, John R. Humphrey, Dennis W. Prather, Mark S. Mirotznik. 269-270 [doi]
- A Pipelined SoPC Architecture for 2.5 Gbps Network ProcessingCiaran Toal, Sakir Sezer, Xing Yu. 271-272 [doi]
- A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAsAbdsamad Benkrid, Khaled Benkrid, Danny Crookes. 273-275 [doi]
- Recon .gurable High Resolution Network CameraAndrey Filippov. 276-277 [doi]
- Application of Task Concurrency Management on Dynamically Reconfigurable Hardware PlatformsJavier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor. 278-279 [doi]
- A Logic Based Hardware Development EnvironmentS. Belkacemi, Khaled Benkrid, Danny Crookes. 280-281 [doi]
- Standardizing the Performance Assessment of Reconfigurable Processor ArchitecturesLesley Shannon, Paul Chow. 282-283 [doi]
- An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAsAlex K. Jones, Prithviraj Banerjee. 284-285 [doi]
- A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NICRanjesh G. Jaganathan, Keith D. Underwood, Ron R. Sass. 286-287 [doi]
- Fabric-Based Systems: Model, Tools, ApplicationsChristophe Wolinski, Maya Gokhale, Kevin McCabe. 288-289 [doi]
- An Estimation and Simulation Framework for Energy Efficient Design using Platform FPGAsSumit Mohanty, Jingzhao Ou, Viktor K. Prasanna. 290-291 [doi]
- Exploiting Reconfigurable Hardware for Network SecurityShaomeng Li, Jim Torresen, Oddvar Søråsen. 292-293 [doi]
- A Second Generation Embedded Reconfigurable Input Device for Kinetically Challenged PersonsKyprianos Papademetriou, Apostolos Dollas, Stamatios N. Sotiropoulos. 294-295 [doi]
- Performance and Area Modeling of Complete FPGA Designs in the presence of Loop TransformationsK. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz. 296 [doi]
- Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing EnginesJoonseok Park, Pedro C. Diniz. 297-299 [doi]
- Linear Placement for Static / Dynamic Reconfiguration in JBitsVamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan. 300-301 [doi]
- Real-time Extensions to a C-like Hardware Description LanguageTim Todman, Wayne Luk. 302-304 [doi]
- RSA encryption using Extended Modular Arithmetic on the Quicksilver COSM Adaptive Computing MachineKiran Puttegowda, Peter Athanas. 305-307 [doi]
- Kernel Formation in GarpccTim Callahan. 308 [doi]