Using GALS architecture to reduce the impact of long wire delay on FPGA performance - researchr publication

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Xin Jia, Ranga Vemuri. Using GALS architecture to reduce the impact of long wire delay on FPGA performance. In Ting-Ao Tang, editor, Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005. pages 1260-1263, ACM Press, 2005. [doi]

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