An FPGA implementation of low-density parity-check code decoder with multi-rate capability

Lei Yang, Manyuan Shen, Hui Liu, C.-J. Richard Shi. An FPGA implementation of low-density parity-check code decoder with multi-rate capability. In Ting-Ao Tang, editor, Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005. pages 760-763, ACM Press, 2005. [doi]

Abstract

Abstract is missing.