Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling - researchr publication

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Jeng-Liang Tsai, Charlie Chung-Ping Chen. Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. In Ting-Ao Tang, editor, Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005. pages 1168-1171, ACM Press, 2005. [doi]

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