A statistical gate delay model for intra-chip and inter-chip variabilities - researchr publication

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Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera. A statistical gate delay model for intra-chip and inter-chip variabilities. In Hiroto Yasuura, editor, Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003. pages 31-36, ACM, 2003. [doi]

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