Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera. A statistical gate delay model for intra-chip and inter-chip variabilities. In Hiroto Yasuura, editor, Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003. pages 31-36, ACM, 2003. [doi]
@inproceedings{OkadaYO03-0,
title = {A statistical gate delay model for intra-chip and inter-chip variabilities},
author = {Ken-ichi Okada and Kento Yamaoka and Hidetoshi Onodera},
year = {2003},
doi = {10.1145/1119772.1119779},
url = {http://doi.acm.org/10.1145/1119772.1119779},
researchr = {https://researchr.org/publication/OkadaYO03-0},
cites = {0},
citedby = {0},
pages = {31-36},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003},
editor = {Hiroto Yasuura},
publisher = {ACM},
isbn = {0-7803-7660-9},
}