Table of Contents

• Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design ChallengesBiswadip Mitra. 3-4 [doi]
• LSI Design in the 21st Century: Key Changes in Sub-1V Giga-Integration EraKazuo Yano. 5 [doi]
• Electronic Industry on Fire: How to Survive and ThriveAart J. de Geus. 6 [doi]
• Digital WatermarkingMartin F. H. Schuurmans. 7 [doi]
• Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract)Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan. 11-13 [doi]
• System-Level Design of Embedded Media Systems (Tutorial Abstract)Pieter van der Wolf, W. M. Kruijtzer, Jos T. J. van Eijndhoven. 14-15 [doi]
• Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract)Stefan Rusu, Manoj Sachdev, Christer Svensson, B. Nauta. 16-17 [doi]
• Mathematical Methods in VLSI (Tutorial Abstract)M. V. Atre, P. S. Subramanian, H. Narayanan. 18-19 [doi]
• Electronic Testing for SOC Designers (Tutorial Abstract)Vishwani D. Agrawal, Michael L. Bushnell. 20 [doi]
• Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract)Luciano Lavagno, Sujit Dey, Rajesh K. Gupta. 21-23 [doi]
• MEMS: Technology, Design, CAD and Applications (Tutorial Abstract)R. Lal, P. R. Apte, K. N. Bhat, G. Bose, S. Chandra, D. K. Sharma. 24-25 [doi]
• Logic Design of Asynchronous Circuits (Tutorial Abstract)Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside. 26 [doi]
• Evaluating Run-Time Techniques for Leakage Power ReductionDavid Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin. 31-38 [doi]
• Topological Analysis for Leakage Prediction of Digital CircuitsWenjie Jiang, Vivek Tiwari, Erik de la Iglesia, Amit Sinha. 39-44 [doi]
• Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design EnvironmentRahul Kumar, C. P. Ravikumar. 45-50 [doi]
• Estimation of Maximum Power-Up CurrentFei Li, Lei He, Kewal K. Saluja. 51 [doi]
• Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix MethodJoong-Ho Kim, Erdem Matoglu, Jinwoo Choi, Madhavan Swaminathan. 59-64 [doi]
• Dynamic Noise Analysis with Capacitive and Inductive CouplingSeung Hoon Choi, Bipul Chandra Paul, Kaushik Roy. 65-70 [doi]
• Substrate Noise Analysis with Compact Digital Noise Injection and Substrate ModelsMakoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata. 71-76 [doi]
• Efficient Generation of Delay Change Curves for Noise-Aware Static Timing AnalysisKanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu. 77 [doi]
• An Efficient Algorithm for Low Power Pass Transistor Logic SynthesisRupesh S. Shelar, Sachin S. Sapatnekar. 87-92 [doi]
• Design of Asynchronous Controllers with Delay Insensitive InterfaceHiroshi Saito, Alex Kondratyev, Takashi Nanya. 93-98 [doi]
• Synthesis of High Performance Low Power Dynamic CMOS CircuitsDebasis Samanta, Nishant Sinha, Ajit Pal. 99-104 [doi]
• Improvement of ASIC Design ProcessesVineet Sahula, C. P. Ravikumar, D. Nagchoudhuri. 105 [doi]
• ETAM++: Extended Transition Activity Measure for Low Power Address Bus DesignsHaris Lekatsas, Jörg Henkel. 113-120 [doi]
• Weight-Based Bus-Invert Coding for Low-Power ApplicationsRung-Bin Lin, Chi-Ming Tsai. 121-125 [doi]
• Software-Only Bus Encoding Techniques for an Embedded SystemWei-Chung Cheng, Jian-Lin Liang, Massoud Pedram. 126-131 [doi]
• Interconnect Energy Dissipation in High-Speed ULSI CircuitsPayam Heydari, Massoud Pedram. 132 [doi]
• Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability VerificationN. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell. 141 [doi]
• Losses in Multilevel Crossover in VLSI InterconnectsP. K. Datta, S. Sanyal, D. Bhattacharya. 142-146 [doi]
• Rational ABCD Modeling of High-Speed InterconnectsQinwei Xu, Pinaki Mazumder. 147 [doi]
• Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and OptimizationKuo-Hsing Cheng, Shun-Wen Cheng. 155-159 [doi]
• A New Synthesis of Symmetric FunctionsHafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya. 160-165 [doi]
• Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLAHiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada. 166-171 [doi]
• Register Transfer Operation Analysis during Data Path VerificationD. Sarkar. 172 [doi]
• A Real Delay Switching Activity Simulator Based on Petri Net ModelingAshok K. Murugavel, N. Ranganathan. 181-186 [doi]
• Switching Activity Estimation of Large Circuits using Multiple Bayesian NetworksSanjukta Bhanja, N. Ranganathan. 187-192 [doi]
• Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS CircuitsDebasis Samanta, Ajit Pal. 193-198 [doi]
• Minimizing Energy Consumption for High-Performance ProcessingEric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti. 199 [doi]
• PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay AnalysisA. B. Bhattacharyya, Shrutin Ulman. 207-212 [doi]
• A Parallel and Accelerated Circuit Simulator with Precise AccuracyPeter M. Lee, Shinji Ito, Takeaki Hashimoto, Junji Sato, Tomomasa Touma, Goichi Yokomizo. 213-218 [doi]
• Timing Yield Calculation Using an Impulse-Train ApproachSrinath R. Naidu. 219-224 [doi]
• Implant Dose Sensitivity of 0.1µm CMOS Inverter DelayH. C. Srinivasaiah, Navakanta Bhat. 225 [doi]
• Exploring the Number of Register Windows in ASIP SynthesisVishal P. Bhatt, M. Balakrishnan, Anshul Kumar. 233-238 [doi]
• Architecture Implementation Using the Machine Description Language LISAOliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr. 239-244 [doi]
• A Framework for Design Space Exploration of Parameterized VLSI SystemsGiuseppe Ascia, Vincenzo Catania, Maurizio Palesi. 245-250 [doi]
• An Evolutionary Scheme for Cosynthesis of Real-Time SystemsS. Chakraverty, C. P. Ravikumar, D. Roy Choudhuri. 251 [doi]
• Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power DesignKanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi. 261-267 [doi]
• A Power Minimization Technique for Arithmetic Circuits by Cell SelectionMasanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura. 268-273 [doi]
• Functional Partitioning for Low Power Distributed Systems of Systems-on-a-ChipYunsi Fei, Niraj K. Jha. 274-281 [doi]
• An Architectural Level Energy Reduction Technique For Deep-Submicron Cache MemoriesTohru Ishihara, Kunihiro Asada. 282-287 [doi]
• Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank MemoriesVictor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu. 288 [doi]
• Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOIS. Natarajan, A. Marshall. 297-298 [doi]
• Transistor Flaring in Deep Submicron-Design ConsiderationsVipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh. 299-304 [doi]
• A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSIShuzhou Fang, Zeyi Wang, Xianlong Hong. 305-310 [doi]
• Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov MethodsQ. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh. 311-316 [doi]
• Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing LatchesMaryam Shojaei Baghini, Madhav P. Desai. 317 [doi]
• Embedded Tutorial: General Architectural Concepts for IP Core Re-UseP. Klapproth. 325 [doi]
• Framework for Synthesis of Virtual PipelinesSrinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri. 326-331 [doi]
• Automatic Model Refinement for Fast Architecture ExplorationJunyu Peng, Samar Abdi, Daniel Gajski. 332-337 [doi]
• Software Pipelining for Coarse-Grained Reconfigurable Instruction Set ProcessorsFrancisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck. 338-344 [doi]
• Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAsLi Shang, Niraj K. Jha. 345 [doi]
• A Design of Analog C-Matrix Circuits Used for Signal/Data ProcessingTakayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yoshida. 355-359 [doi]
• A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip EnvironmentDebapriya Sahu. 360-365 [doi]
• Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization ApproachBiranchinath Sahu, Aloke K. Dutta. 366-371 [doi]
• Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven RoutingJens Lienig, Goeran Jerke, Thorsten Adler. 372 [doi]
• Buffered Routing Tree Construction under Buffer Placement BlockagesWei Chen, Massoud Pedram, Premal Buch. 381-386 [doi]
• Stairway Compaction using Corner Block List and Its Applications with Rectilinear BlocksYuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu. 387-392 [doi]
• An Adaptive Interconnect-Length Driven PlacerChi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin. 393-398 [doi]
• Net Clustering Based Macrocell PlacementStelian Alupoaei, Srinivas Katkoori. 399 [doi]
• High-Level Synthesis with SIMD UnitsVijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac. 407-413 [doi]
• A Heuristic for Clock Selection in High-Level SynthesisJ. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir. 414-419 [doi]
• Design for Verification at the Register Transfer LevelIndradeep Ghosh, Krishna Sekar, Vamsi Boppana. 420-425 [doi]
• Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch DesignGabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya. 426 [doi]
• VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension SchemeKavish Seth, S. Srinivasan. 435-440 [doi]
• An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit ImplementationHak-soo Yu, Jacob A. Abraham. 441-446 [doi]
• Architecture and Design of a High Performance SRAM for SOC DesignShobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka Phani, Ansuman Rout. 447-451 [doi]
• VLSI Architecture for a Flexible Motion Estimation with ParametersJinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 452-457 [doi]
• Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description LanguagePrabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau. 458 [doi]
• Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC LayoutsYukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita. 467-472 [doi]
• An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global RoutingJingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu. 473-478 [doi]
• Simultaneous Circuit Transformation and RoutingHiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita. 479-483 [doi]
• Probabilistic Analysis of Rectilinear Steiner TreesChunhong Chen. 484-488 [doi]
• Power Supply Noise Aware Floorplanning and Decoupling Capacitance PlacementShiyou Zhao, Kaushik Roy, Cheng-Kok Koh. 489 [doi]
• A Novel Method to Improve the Test Efficiency of VLSI TestsHailong Cui, Sharad C. Seth, Shashank K. Mehta. 499-504 [doi]
• On Test Scheduling for Core-Based SOCsSandeep Koranne. 505-510 [doi]
• Constraint Driven Pin Mapping for Concurrent SOC TestingYu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy. 511-516 [doi]
• Identifying Redundant Wire Replacements for Synthesis and VerificationKatarzyna Radecka, Zeljko Zilic. 517-523 [doi]
• Property-Specific Testbench Generation for Guided SimulationAarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi. 524 [doi]
• A New Divide and Conquer Method for Achieving High Speed Division in HardwareMurali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan. 535-540 [doi]
• SWASAD: An ASIC Design for High Speed DNA Sequence MatchingTony Han, Sri Parameswaran. 541-546 [doi]
• Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video DecoderMartin Palkovic, Miguel Miranda, Kristof Denolf, Peter Vos, Francky Catthoor. 547-552 [doi]
• A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image CommunicationDebashis Panigrahi, Clark N. Taylor, Sujit Dey. 553 [doi]
• Efficient Macromodeling for On-Chip InterconnectsQinwei Xu, Pinaki Mazumder. 561-566 [doi]
• An Upper Bound for 3D Slicing FloorplansSilke Salewski, Erich Barke. 567-572 [doi]
• System-Level Point-to-Point Communication Synthesis using Floorplanning InformationJingcao Hu, Yangdong Deng, Radu Marculescu. 573-579 [doi]
• Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire SizingChristoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky. 580 [doi]
• Multiple Faults: Modeling, Simulation and TestYong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja. 592-597 [doi]
• Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) SwitchSubhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik. 598-603 [doi]
• Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BISTNadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski. 604 [doi]
• Low Power Solution for Wireless ApplicationsSornavalli Ramanathan, Rituparna Mandal. 615-618 [doi]
• Address Code and Arithmetic Optimizations for Embedded SystemsJ. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, Mahmut T. Kandemir. 619-624 [doi]
• Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) ApplicationsYong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo. 625-630 [doi]
• Strategies for Improving Data Locality in Embedded ApplicationsN. E. Crosbie, Mahmut T. Kandemir, Ibrahim Kolcu, J. Ramanujam, Alok N. Choudhary. 631 [doi]
• On Routing Demand and Congestion Estimation for FPGAsShankar Balachandran, PariVallal Kannan, Dinesh Bhatia. 639-646 [doi]
• Layout-Driven Timing Optimization by Generalized De Morgan TransformSupratik Chakraborty, Rajeev Murgai. 647-654 [doi]
• Reducing Library Development Cycle Time through an Optimum Layout Create FlowRituparna Mandal, Dibyendu Goswami, Arup Dash. 655-660 [doi]
• A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan DesignEvangeline F. Y. Young, Chris C. N. Chu, M. L. Ho. 661 [doi]
• Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate AreaSamir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das. 671-676 [doi]
• A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan CircuitsIrith Pomeranz, Sudhakar M. Reddy. 677-682 [doi]
• Optimization of Test Accesses with a Combined BIST and External Test SchemeMakoto Sugihara, Hiroto Yasuura. 683-688 [doi]
• Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri. 689 [doi]
• Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded SystemsDexin Li, Pai H. Chou, Nader Bagherzadeh. 697-704 [doi]
• Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive TasksAnupam Datta, Sidharth Choudhury, Anupam Basu. 705-710 [doi]
• Input Space Adaptive Embedded Software SynthesisWeidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha. 711-718 [doi]
• Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded SystemsJiong Luo, Niraj K. Jha. 719 [doi]
• Improved SAT-Based Bounded Reachability AnalysisMalay K. Ganai, Adnan Aziz. 729-734 [doi]
• Open Computation Tree Logic for Formal Verification of ModulesPallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti. 735-740 [doi]
• RTL-Datapath Verification using Integer Linear ProgrammingRaik Brinkmann, Rolf Drechsler. 741-746 [doi]
• Verification of an Industrial CC-NUMA ServerRajarshi Mukherjee, Yozo Nakayama, Toshiya Mima. 747 [doi]
• Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit SettingSagar S. Sabade, D. M. H. Walker. 755-760 [doi]
• Divide-and-Conquer IDDQ Testing for Core-Based System ChipsC. P. Ravikumar, Rahul Kumar. 761-766 [doi]
• Path Delay Fault Test Generation for Standard Scan Designs Using State TuplesYun Shao, Irith Pomeranz, Sudhakar M. Reddy. 767-772 [doi]
• Test Solution for OTA Based Analog CircuitsBaidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi. 773 [doi]
• Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-SiliconKaranth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji. 781-788 [doi]
• Development of ASIC Chip-Set for High-End Network Processing Application-A Case StudySanjeev Patel. 789-794 [doi]
• IEEE 1394a_2000 Physical Layer ASICRanjit Yashwante, Bhalchandra Jahagirdar. 795-800 [doi]
• Definition, Design & Development of the IXE2424 Network Switch/Router ASICT. Datta, C. S. Muralidharan. 801-802 [doi]