Jagdish C. Rao - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 8 from 8

2009

Clock gating effectiveness metrics: Applications to power optimizationJithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao. isqed 2009: 482-487 [doi]

Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and SolutionsR. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao. vlsid 2009: 525-530 [doi]

2008

Clock gating for power optimization in ASIC design cycle theory & practiceSukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao. islped 2008: 307-308 [doi]

2006

Enabling Quality and Schedule Predictability in SoC Design using HandoffQCBhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao. isqed 2006: 769-774 [doi]

2002

Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-SiliconKaranth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji. vlsid 2002: 781-788 [doi]

2000

A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor CoresKarthikeyan Madathil, Jagdish C. Rao, Subash G. Chandar, Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar. vlsid 2000: 468 [doi]

1999

A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron TechnologyAvinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash G. Chandar. iccd 1999: 340-347 [doi]

A Design-in Methodology to Ensure First Time Success of Complex Digital Signal ProcessorsAvinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar. vlsid 1999: 346-349 [doi]

Sign in or sign up to see more results.

runs on WebDSL