Abstract is missing.
- Towards a green electronic world: a collaborative approachJaswinder Ahuja. 1-2 [doi]
- Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuitsHiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye. 3-8 [doi]
- Optimal technology selection for minimizing energy and variability in low voltage applicationsMingoo Seok, Dennis Sylvester, David Blaauw. 9-14 [doi]
- Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technologyHiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara. 15-20 [doi]
- Enhancing ::::beneficial jitter:::: using phase-shifted clock distributionDong Jiao, Jie Gu, Pulkit Jain, Chris H. Kim. 21-26 [doi]
- Dynamic virtual ground voltage estimation for power gatingHao Xu, Ranga Vemuri, Wen-Ben Jone. 27-32 [doi]
- A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flopsMohammad Ghasemazar, Behnam Amelifard, Massoud Pedram. 33-38 [doi]
- Power-gating-aware high-level synthesisEunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin. 39-44 [doi]
- A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizingTai-Hsuan Wu, Lin Xie, Azadeh Davoodi. 45-50 [doi]
- Multiple power-gating domain (multi-VGND) architecture for improved leakage power reductionAshoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 51-56 [doi]
- A multi-story power delivery technique for 3D integrated circuitsPulkit Jain, Tae-Hyoung Kim, John Keane, Chris H. Kim. 57-62 [doi]
- Energy harvesting photodiodes with integrated 2D diffractive storage capacitanceNathaniel J. Guilar, Erin G. Fong, Travis Kleeburg, Diego R. Yankelevich, Rajeevan Amirtharajah. 63-68 [doi]
- Reducing wakeup latency and energy of MTCMOS circuits via keeper insertionCharbel J. Akl, Magdy A. Bayoumi. 69-74 [doi]
- Low-power high-accuracy timing systems for efficient duty cyclingThomas Schmid, Jonathan Friedman, Zainul Charbiwala, Young H. Cho, Mani B. Srivastava. 75-80 [doi]
- An expected-utility based approach to variation aware VLSI optimization under scarce informationUpavan Gupta, Nagarajan Ranganathan. 81-86 [doi]
- SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemesRouwaida Kanj, Rajiv V. Joshi, Zhou Li, Jente B. Kuang, Hung C. Ngo, Ying Zhou, Weiping Shi, Sani R. Nassif. 87-92 [doi]
- Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variationMaziar Goudarzi, Tohru Ishihara. 93-98 [doi]
- Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and powerKoustav Bhattacharya, Nagarajan Ranganathan. 99-104 [doi]
- Variation-aware gate sizing and clustering for post-silicon optimized circuitsCheng Zhuo, David Blaauw, Dennis Sylvester. 105-110 [doi]
- Error-resilient low-power Viterbi decodersRami A. Abdallah, Naresh R. Shanbhag. 111-116 [doi]
- Increasing minimum operating voltage (V::DDmin::) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillatorsTaro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai. 117-122 [doi]
- Thermal analysis of 8-T SRAM for nano-scaled technologiesMesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy. 123-128 [doi]
- Analyzing static and dynamic write margin for nanometer SRAMsJiajing Wang, Satyanand Nalam, Benton H. Calhoun. 129-134 [doi]
- Power management solutions for computer systems and datacentersKarthick Rajamani, Charles Lefurgy, Soraya Ghiasi, Juan Rubio, Heather Hanson, Tom W. Keller. 135-136 [doi]
- Low power design under parameter variationsSwarup Bhunia, Kaushik Roy. 137-138 [doi]
- Power management from cores to datacenters: where are we going to get the next ten-fold improvements?Parthasarathy Ranganathan. 139-140 [doi]
- Caching for bursts (C-Burst): let hard disks sleep well and work energeticallyFeng Chen, Xiaodong Zhang. 141-146 [doi]
- 3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encodingMuhammad Shafique, Lars Bauer, Jörg Henkel. 147-152 [doi]
- Energy conservation by adaptive feature loading for mobile content-based image retrievalKarthik Kumar, Yamini Nimmagadda, Yu-Ju Hong, Yung-Hsiang Lu. 153-158 [doi]
- Extending the lifetime of media recorders constrained by battery and flash memory sizeYounghyun Kim, Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Nam Ik Cho. 159-164 [doi]
- Proactive temperature management in MPSoCsAyse Kivilcim Coskun, Tajana Simunic Rosing, Kenny C. Gross. 165-170 [doi]
- Entry control in network-on-chip for memory power reductionDongwook Lee, Sungjoo Yoo, Kiyoung Choi. 171-176 [doi]
- PowerAntz: distributed power sharing strategy for network on chipSuman Kalyan Mandal, Rabi N. Mahapatra. 177-182 [doi]
- System implications of integrated photonicsNorman P. Jouppi. 183-184 [doi]
- Design of dual threshold voltages asynchronous circuitsBehnam Ghavami, Hossein Pedram. 185-188 [doi]
- O:::2:::C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessorsSwaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy. 189-192 [doi]
- Low power high bandwidth amplifier with RC Miller and gain enhanced feedforward compensationShagun Bajoria, Vineet Kumar Singh, Raju Kunde, Chetan D. Parikh. 193-196 [doi]
- Single stage static level shifter design for subthreshold to I/O voltage conversionYi-Shiang Lin, Dennis M. Sylvester. 197-200 [doi]
- Power reduction in on-chip interconnection network by serializationMadan Arvind, Bharadwaj Amrutur. 201-204 [doi]
- A probabilistic technique for full-chip leakage estimationShaobo Liu, Qinru Qiu, Qing Wu. 205-208 [doi]
- Bus encoding for simultaneous delay and energy optimizationJingyi Zhang, Qing Wu, Qinru Qiu. 209-212 [doi]
- Frequency planning for multi-core processors under thermal constraintsMichael Kadin, Sherief Reda. 213-216 [doi]
- Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuitsAndrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino. 217-220 [doi]
- Variability of flip-flop timing at sub-threshold voltagesNiklas Lotze, Maurits Ortmanns, Yiannos Manoli. 221-224 [doi]
- Low power current mode receiver with inductive input impedanceMarshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma. 225-228 [doi]
- Analytical results for design space exploration of multi-core processors employing thread migrationRavishankar Rao, Sarma B. K. Vrudhula, Krzysztof S. Berezowski. 229-232 [doi]
- A physical level study and optimization of CAM-based checkpointed register alias tableElham Safi, Andreas Moshovos, Andreas G. Veneris. 233-236 [doi]
- A tutorial on test powerVishwani D. Agrawal. 237-238 [doi]
- Power delivery for high performance microprocessorsSrikanth Balasubramanian. 239-240 [doi]
- Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extensionHamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami. 241-246 [doi]
- Energy-efficient MESI cache coherence with pro-active snoop filtering for multicore microprocessorsAvadh Patel, Kanad Ghose. 247-252 [doi]
- A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codesJie Jin, Chi-Ying Tsui. 253-258 [doi]
- A secure and low-energy logic style using charge recovery approachMehrdad Khatir, Amir Moradi, Alireza Ejlali, Mohammad T. Manzuri Shalmani, Mahmoud Salmasizadeh. 259-264 [doi]
- Word-interleaved cache: an energy efficient data cache architectureT. Venkata Kalyan, Madhu Mutyam. 265-270 [doi]
- Optimal power and noise allocation for analog and digital sections of a low power radio receiverKannan Aryaperumal Sankaragomathi, Manodipan Sahoo, Satyam Dwivedi, Bharadwaj S. Amrutur, Navakanta Bhat. 271-276 [doi]
- Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequenciesXuning Chen, Gu-Yeon Wei, Li-Shiuan Peh. 277-282 [doi]
- On the power efficiency of cascode compensation over Miller compensation in two-stage operational amplifiersHamed Aminzadeh, Khalil Mafinezhad. 283-288 [doi]
- A 1-V piecewise curvature-corrected CMOS bandgap referenceJing-hu Li, Yu-nan Fu, Yong-sheng Wang. 289-294 [doi]
- A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuningDepak Balemarthy, Roy Paily. 295-300 [doi]
- Innovations to extend CMOS nano-transistors to the limitTahir Ghani. 301-302 [doi]
- Penalty for power reduction -: performance or schedule or yield?Bodhisatya Sarker, Jaswinder Ahuja, Arijit Dutta, Srinath D., Kaip Sridhar, Radhakrishnan Nair, Jayant Lahiri. 303-304 [doi]
- SOC designs in the energy conscious eraSrikanth Jadcherla. 305-306 [doi]
- Clock gating for power optimization in ASIC design cycle theory & practiceSukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao. 307-308 [doi]
- Simultaneous optimization of battery-aware voltage regulator scheduling with dynamic voltage and frequency scalingYoungjin Cho, Younghyun Kim, Yongsoo Joo, Kyungsoo Lee, Naehyuck Chang. 309-314 [doi]
- Expected system energy consumption minimization in leakage-aware DVS systemsJian-Jia Chen, Lothar Thiele. 315-320 [doi]
- Hybrid dynamic thermal management based on statistical characteristics of multimedia applicationsInchoon Yeo, Eun Jung Kim. 321-326 [doi]
- Advances in low power verificationJanick Bergeron. 327-328 [doi]
- A framework for energy consumption based design space exploration for wireless sensor nodesSonali Chouhan, M. Balakrishnan, Ranjan Bose. 329-334 [doi]
- Full-system chip multiprocessor power evaluations using FPGA-based emulationAbhishek Bhattacharjee, Gilberto Contreras, Margaret Martonosi. 335-340 [doi]
- Noninvasive leakage power tomography of integrated circuits by compressive sensingDavood Shamsi, Petros Boufounos, Farinaz Koushanfar. 341-346 [doi]
- Low power chips: a fabless asic perspectiveShashank Bhonge, Vamsi Boppana. 347-348 [doi]
- On leakage currents: sources and reduction for transistors, gates, memories and digital systemsWolfgang Nebel, Domenik Helms. 349-350 [doi]
- Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architecturesNiranjan Soundararajan, Narayanan Vijaykrishnan, Anand Sivasubramaniam. 351-356 [doi]
- Instruction-driven clock scheduling with glitch mitigationGu-Yeon Wei, David Brooks, Ali Durlov Khan, Xiaoyao Liang. 357-362 [doi]
- Thread fusionJosé González, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Ryan Rakvic, Antonio González. 363-368 [doi]
- Power-efficient clustering via incomplete bypassingEric P. Villasenor, Daeho Seo, Mithuna Thottethodi. 369-374 [doi]
- Lazy instruction scheduling: keeping performance, reducing powerAli Mahjur, Mahmud Taghizadeh, Amir-Hossein Jahangir. 375-380 [doi]
- On the rules of low-power design (and how to break them)Todd M. Austin. 381-382 [doi]
- Next-generation power-aware designTakayasu Sakurai. 383-384 [doi]