Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura. A Power Minimization Technique for Arithmetic Circuits by Cell Selection. In Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11 January 2002, Bangalore, India. pages 268-273, IEEE Computer Society, 2002. [doi]
Abstract is missing.