Table of Contents

• Panel: The Electronics Industry Supply Chain: Who Will Do What?Rita Glover, Marc Halpern, Rich Becks, Richard Kubin, Henry Jurgens, Rick Cassidy, Ted Vucurevich. 1-2 [doi]
• Future Performance Challenges in Nanometer DesignDennis Sylvester, Himanshu Kaul. 3-8 [doi]
• IC Design in High-Cost Nanometer-Technologies EraWojciech Maly. 9-14 [doi]
• LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip DesignsKanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana. 15-20 [doi]
• Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive ProtocolsTiberiu Chelcea, Steven M. Nowick. 21-26 [doi]
• Latency-Driven Design of Multi-Purpose Systems-On-ChipSeapahn Meguerdichian, Milenko Drinic, Darko Kirovski. 27-30 [doi]
• Estimation of Speed, Area, and Power of Parameterizable, Soft IPJagesh V. Sanghavi, Albert Wang. 31-34 [doi]
• Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid EnginesDong Wang, Pei-Hsin Ho, Jiang Long, James H. Kukula, Yunshan Zhu, Hi-Keung Tony Ma, Robert F. Damiano. 35-40 [doi]
• Scalable Hybrid Verification of Complex MicroprocessorsMaher N. Mneimneh, Fadi A. Aloul, Christopher T. Weaver, Saugata Chatterjee, Karem A. Sakallah, Todd M. Austin. 41-46 [doi]
• Symbolic RTL SimulationAlfred Kölbl, James H. Kukula, Robert F. Damiano. 47-52 [doi]
• A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access ControllersBulent I. Dervisoglu. 53-58 [doi]
• Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-ChipWei-Cheng Lai, Kwang-Ting Cheng. 59-64 [doi]
• Test Strategies for BIST at the Algorithmic and Register-Transfer LevelsKelly A. Ockunzzi, Christos A. Papachristou. 65-70 [doi]
• Panel: The Next HDL: If C++ is the Answer, What was the Question?Rajesh K. Gupta, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont. 71-72 [doi]
• Reticle Enhancement Technology: Implications and Challenges for Physical DesignWarren Grobman, M. Thompson, R. Wang, C. Yuan, Ruiqi Tian, E. Demircan. 73-78 [doi]
• Enabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules and Design Rule CheckingLars Liebmann, Jennifer Lund, Fook-Luen Heng, Ioana Graur. 79-84 [doi]
• Layout Design Methodologies for Sub-Wavelength ManufacturingMichael L. Rieger, Jeffrey P. Mayhew, Sridhar Panchapakesan. 85-88 [doi]
• Adoption of OPC and the Impact on Design and LayoutFranklin M. Schellenberg, Olivier Toublan, Luigi Capodieci, Bob Socha. 89-92 [doi]
• A Practical Application of Full-Feature Alternating Phase-Shifting Technology for a Phase-Aware Standard-Cell Design FlowMichael Sanie, Michel Côté, Philippe Hurat, Vinod Malhotra. 93-96 [doi]
• Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring TechniquesChih-Wei Jim Chang, Kai Wang, Malgorzata Marek-Sadowska. 97-102 [doi]
• An Algorithm for Bi-Decomposition of Logic FunctionsAlan Mishchenko, Bernd Steinbach, Marek A. Perkowski. 103-108 [doi]
• Factoring and Recognition of Read-Once Functions using Cographs and NormalityMartin Charles Golumbic, Aviad Mintz, Udi Rotics. 109-114 [doi]
• Logic Minimization using Exclusive OR GatesValentina Ciriani. 115-120 [doi]
• Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication SystemsJafar Savoj, Behzad Razavi. 121-126 [doi]
• A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADCDavid Goren, Eliyahu Shamsaev, Israel A. Wagner. 127-132 [doi]
• Behavioral Partitioning in the Synthesis of Mixed Analog-Digital SystemsSree Ganesan, Ranga Vemuri. 133-138 [doi]
• Efficient DDD-based Symbolic Analysis of Large Linear Analog CircuitsWim Verhaegen, Georges G. E. Gielen. 139-144 [doi]
• Random Limited-Scan to Improve Random Pattern Testing of Scan CircuitsIrith Pomeranz. 145-150 [doi]
• Test Volume and Application Time Reduction Through Scan Chain ConcealmentIsmet Bayraktaroglu, Alex Orailoglu. 151-155 [doi]
• An Approach to Test Compaction for Scan Circuits that Enhances At-Speed TestingIrith Pomeranz, Sudhakar M. Reddy. 156-161 [doi]
• Generating Efficient Tests for Continuous ScanSying-Jyan Wang, Sheng-Nan Chiou. 162-165 [doi]
• Combining Low-Power Scan Testing and Test Data Compression for System-on-a-ChipAnshuman Chandra, Krishnendu Chakrabarty. 166-169 [doi]
• Panel: Your Core - My Problem? Integration and Verification of IPGabe Moretti, Tim Hopes, Ramesh Narayanaswamy, Nanette Collins, Dave Kelf, Tom Anderson, Janick Bergeron, Ashish Dixit, Peter Flake. 170-171 [doi]
• A Quick Safari Through the Reconfiguration JunglePatrick Schaumont, Ingrid Verbauwhede, Kurt Keutzer, Majid Sarrafzadeh. 172-177 [doi]
• Re-Configurable Computing in WirelessBill Salefski, Levent Caglar. 178-183 [doi]
• Hardware/Software Instruction Set Configurability for System-on-Chip ProcessorsAlbert Wang, Earl Killian, Dror E. Maydan, Chris Rowen. 184-188 [doi]
• A Practical Methodology for Early Buffer and Wire Resource AllocationCharles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia. 189-194 [doi]
• Creating and Exploiting Flexibility in Steiner TreesElaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh. 195-198 [doi]
• Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise ConstraintKevin M. Lepak, Irwan Luwandi, Lei He. 199-202 [doi]
• On Optimum Switch Box Designs for 2-D FPGAsHongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung. 203-208 [doi]
• Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian NetworksSanjukta Bhanja, N. Ranganathan. 209-214 [doi]
• A Static Estimation Technique of Power Sensitivity in Logic CircuitsTaewhan Kim, Ki-Seok Chung, Chien-Liang Liu. 215-219 [doi]
• JouleTrack - A Web Based Tool for Software Energy ProfilingAmit Sinha, Anantha Chandrakasan. 220-225 [doi]
• Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW MicroprocessorsMiroslav N. Velev, Randal E. Bryant. 226-231 [doi]
• Circuit-based Boolean ReasoningAndreas Kuehlmann, Malay K. Ganai, Viresh Paruthi. 232-237 [doi]
• Checking Equivalence for Partial ImplementationsChristoph Scholl, Bernd Becker. 238-243 [doi]
• Validating the Intel Pentium 4 MicroprocessorBob Bentley. 244-248 [doi]
• Nuts and Bolts of Core and SoC VerificationKen Albin. 249-252 [doi]
• Teaching Future Verification Engineers: The Forgotten Side of Logic DesignFüsun Özgüner, Duane W. Marhefka, Joanne DeGroat, Bruce Wile, Jennifer Stofer, Lyle Hanrahan. 253-255 [doi]
• SoC Integration of Reusable Baseband Bluetooth IPTorbjörn Grahm, Barry Clark. 256-261 [doi]
• One-chip Bluetooth ASIC ChallengesPaul T. M. van Zeijl. 262 [doi]
• Transformations for the Synthesis and Optimization of Asynchronous Distributed ControlMichael Theobald, Steven M. Nowick. 263-268 [doi]
• Speculation Techniques for High Level Synthesis of Control Intensive DesignsSumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau. 269-272 [doi]
• Parallelizing DSP Nested Loops on Reconfigurable Architectures using Data Context SwitchingKiran Bondalapati. 273-276 [doi]
• Using Symbolic Algebra in Algorithmic Level DSP SynthesisArmita Peymandoust, Giovanni De Micheli. 277-282 [doi]
• Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore AnalysisClayton B. McDonald, Randal E. Bryant. 283-288 [doi]
• A New Gate Delay Model for Simultaneous Switching and Its ApplicationsLiang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer. 289-294 [doi]
• Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI CircuitsGeng Bai, Sudhakar Bobba, Ibrahim N. Hajj. 295-300 [doi]
• Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port MemoriesChi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu. 301-306 [doi]
• Improving Bus Test Via I::DDT:: and Boundary ScanShih-yu Yang, Christos A. Papachristou, Massood Tabib-Azar. 307-312 [doi]
• Fault Characterizations and Design-for-Testability Technique for Detecting I::DDQ:: Faults in CMOS/BiCMOS CircuitsKaamran Raahemifar, Majid Ahmadi. 313-316 [doi]
• Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor CoresLi Chen, Xiaoliang Bai, Sujit Dey. 317-320 [doi]
• Panel: (When) Will FPGAs Kill ASICs?Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen. 321-322 [doi]
• Inductance 101: Modeling and ExtractionMichael W. Beattie, Lawrence T. Pileggi. 323-328 [doi]
• Inductance 101: Analysis and Design IssuesKaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao. 329-334 [doi]
• Modeling Magnetic Coupling for On-Chip InterconnectMichael W. Beattie, Lawrence T. Pileggi. 335-340 [doi]
• Min/max On-Chip Inductance Models and Delay MetricsYi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi. 341-346 [doi]
• Utilizing Memory Bandwidth in DSP Embedded ProcessorsCatherine H. Gebotys. 347-352 [doi]
• Address Code Generation for Digital Signal ProcessorsSathishkumar Udayanarayanan, Chaitali Chakrabarti. 353-358 [doi]
• Reducing Memory Requirements of Nested Loops for Embedded SystemsJ. Ramanujam, Jinpyo Hong, Mahmut T. Kandemir, Amit Narayan. 359-364 [doi]
• Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive ApplicationsPer Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas. 365-370 [doi]
• A New Structural Pattern Matching Algorithm for Technology MappingMin Zhao, Sachin S. Sapatnekar. 371-376 [doi]
• Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar EffectShrirang K. Karandikar, Sachin S. Sapatnekar. 377-382 [doi]
• Latency and Latch Count Minimization in Wave Steered CircuitsAmit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska. 383-388 [doi]
• Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA MappingJason Cong, Michail Romesis. 389-394 [doi]
• Application of Constraint-Based Heuristics in Collaborative DesignJuan Antonio Carballo, Stephen W. Director. 395-400 [doi]
• A Universal Client for Distributed Networked Design and ComputingFranc Brglez, Hemang Lavana. 401-406 [doi]
• Hypermedia-Aided DesignDarko Kirovski, Milenko Drinic, Miodrag Potkonjak. 407-412 [doi]
• A Framework for Object Oriented Hardware Specification, Verification, and SynthesisTommy Kuhn, Tobias Oppold, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai. 413-418 [doi]
• Panel: When Will the Analog Design Flow Catch Up with Digital Methodology?Georges G. E. Gielen, Mike Sottak, Mike Murray, Linda Kaye, Maria del Mar Hershenson, Kenneth S. Kundert, Philippe Magarshack, Akria Matsuzawa, Ronald A. Rohrer, Ping Yang. 419 [doi]
• Achieving 550Mhz in an ASIC MethodologyDavid G. Chinnery, Borivoje Nikolic, Kurt Keutzer. 420-425 [doi]
• A Semi-Custom Design Flow in High-Performance Microprocessor DesignGregory A. Northrop, Pong-Fei Lu. 426-431 [doi]
• Reducing the Frequency Gap Between ASIC and Custom Designs: A Custom PerspectiveStephen E. Rich, Matthew J. Parker, Jim Schwartz. 432-437 [doi]
• Low-Energy Intra-Task Voltage Scheduling Using Static Timing AnalysisDongkun Shin, Jihong Kim, Seongsoo Lee. 438-443 [doi]
• Battery-Aware Static Scheduling for Distributed Real-Time Embedded SystemsJiong Luo, Niraj K. Jha. 444-449 [doi]
• An Approach to Incremental Design of Distributed Embedded SystemsPaul Pop, Petru Eles, Traian Pop, Zebo Peng. 450-455 [doi]
• Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path CircuitsZhan Yu, Meng-Lin Yu, Alan N. Willson Jr.. 456-461 [doi]
• Improved Merging of Datapath Operators using Information Content and Required Precision AnalysisAnmol Mathur, Sanjeev Saluja. 462-467 [doi]
• Digital Filter Synthesis Based on Minimal Signed Digit RepresentationIn-Cheol Park, Hyeong-Ju Kang. 468-473 [doi]
• Publicly Detectable Techniques for the Protection of Virtual ComponentsGang Qu. 474-479 [doi]
• Watermarking of SAT using Combinatorial Isolation LemmasRupak Majumdar, Jennifer L. Wong. 480-485 [doi]
• Watermarking Graph Partitioning SolutionsGregory Wolfe, Jennifer L. Wong, Miodrag Potkonjak. 486-489 [doi]
• Hardware MeteringFarinaz Koushanfar, Gang Qu. 490-493 [doi]
• Technical Visualizations in VLSI DesignPhillip Restle. 494-499 [doi]
• Using Texture Mapping with Mipmapping to Render a VLSI LayoutJeff Solomon, Mark Horowitz. 500-505 [doi]
• Web-based Algorithm AnimationMarc Najork. 506-511 [doi]
• Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded ProcessorsPeter Petrov, Alex Orailoglu. 512-517 [doi]
• Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-ChipDamien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed Amine Jerraya. 518-523 [doi]
• Dynamic Voltage Scaling and Power Management for Portable SystemsTajana Simunic, Luca Benini, Andrea Acquaviva, Peter W. Glynn, Giovanni De Micheli. 524-529 [doi]
• Chaff: Engineering an Efficient SAT SolverMatthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, Sharad Malik. 530-535 [doi]
• Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image ComputationAarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar. 536-541 [doi]
• SATIRE: A New Incremental Satisfiability EngineJesse Whittemore, Joonyoung Kim, Karem A. Sakallah. 542-545 [doi]
• A Framework for Low Complexity Static LearningEmil Gizdarski, Hideo Fujiwara. 546-549 [doi]
• Fast Power/Ground Network Optimization Based on Equivalent Circuit ModelingSheldon X.-D. Tan, C.-J. Richard Shi. 550-554 [doi]
• An Interconnect Energy Model Considering Coupling EffectsTaku Uchino, Jason Cong. 555-558 [doi]
• Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative MethodsTsung-Hao Chen, Charlie Chung-Ping Chen. 559-562 [doi]
• Using Conduction Modes Basis Functions for Efficient Electromagnetic Analysis of On-Chip and Off-Chip InterconnectLuca Daniel, Alberto L. Sangiovanni-Vincentelli, Jacob White. 563-566 [doi]
• Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICsAmir H. Ajami, Kaustav Banerjee, Massoud Pedram, Lukas P. P. P. van Ginneken. 567-572 [doi]
• VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency SynthesizersIreneusz Janiszewski, Bernhard Hoppe, Hermann Meuth. 573-578 [doi]
• Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block CiphersRamesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim. 579-585 [doi]
• MetaCores: Design and Optimization TechniquesSeapahn Meguerdichian, Farinaz Koushanfar, Advait Mogre, Dusan Petranovic, Miodrag Potkonjak. 585-590 [doi]
• Panel: Is Nanometer Design Under Control?Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang. 591-592 [doi]
• A Hardware/Software Co-design Flow and IP Library Based of Simulink:::TM:::Leonardo Maria Reyneri, F. Cucinotta, A. Serra, Luciano Lavagno. 593-598 [doi]
• System-Level Power/Performance Analysis for Embedded Systems DesignAmit Nandi, Radu Marculescu. 599-604 [doi]
• High-level Software Energy Macro-modelingTat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha. 605-610 [doi]
• Model Checking of S3C2400X Industrial Embedded SOC ProductHoon Choi, Byeong-Whee Yun, Yun-Tae Lee, Hyunglae Roh. 611-616 [doi]
• Semi-Formal Test Generation with GenevieveJulia Dushina, Mike Benjamin, Daniel Geist. 617-622 [doi]
• A Transaction-Based Unified Simulation/Emulation Architecture for Functional VerificationMurali Kudlugi, Soha Hassoun, Charles Selvidge, Duaine Pryor. 623-628 [doi]
• Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise ConstraintsAlex Doboli, Ranga Vemuri. 629-634 [doi]
• Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing ArchitecturesKia Bazargan, Seda Ogrenci, Majid Sarrafzadeh. 635-640 [doi]
• Statistical Design Space Exploration for Application-Specific Unit SynthesisDavide Bruni, Alessandro Bogliolo, Luca Benini. 641-646 [doi]
• Static Scheduling of Multiple Asynchronous Domains For Functional VerificationMurali Kudlugi, Charles Selvidge, Russell Tessier. 647-652 [doi]
• Functional Correlation Analysis in Crosstalk Induced Critical Paths IdentificationTong Xiao, Malgorzata Marek-Sadowska. 653-656 [doi]
• An Advanced Timing Characterization Method Using Mode DependencyHakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes. 657-660 [doi]
• Fast Statistical Timing Analysis By Probabilistic Event PropagationJing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic. 661-666 [doi]
• Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based DesignMarco Sgroi, Michael Sheets, Andrew Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli. 667-672 [doi]
• MicroNetwork-Based Integration for SOCsDrew Wingard. 673-677 [doi]
• On-Chip Communication Architecture for OC-768 Network ProcessorsFaraydon Karim, Anh Nguyen, Sujit Dey, Ramesh R. Rao. 678-683 [doi]
• Route Packets, Not Wires: On-Chip Interconnection NetworksWilliam J. Dally, Brian Towles. 684-689 [doi]
• Dynamic Management of Scratch-Pad Memory SpaceMahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh. 690-695 [doi]
• Clustered VLIW Architectures with Predicated SwitchingMargarida F. Jacome, Gustavo de Veciana, Satish Pillai. 696-701 [doi]
• High-Quality Operation Binding for Clustered VLIW DatapathsViktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana. 702-707 [doi]
• Fast Bit-True SimulationHolger Keding, Martin Coors, Olaf Lüthje, Heinrich Meyr. 708-713 [doi]
• Timing Analysis with Crosstalk as Fixpoints on Complete LatticeHai Zhou, Narendra V. Shenoy, William Nicholls. 714-719 [doi]
• Driver Modeling and Alignment for Worst-Case Delay NoiseSupamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo. 720-725 [doi]
• False Coupling Interactions in Static Timing AnalysisRavishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi. 726-731 [doi]
• Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage TechniqueKi-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang. 732-737 [doi]
• Input Space Adaptive Design: A High-level Methodology for Energy and Performance OptimizationWeidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha. 738-743 [doi]
• A:::2:::BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron DesignsJörg Henkel, Haris Lekatsas. 744-749 [doi]
• Coupling-Driven Bus Design for Low-Power Application-Specific SystemsYoungsoo Shin, Takayasu Sakurai. 750-753 [doi]
• Modeling and Minimization of Interconnect Energy Dissipation in Nanometer TechnologiesClark N. Taylor, Sujit Dey, Yi Zhao. 754-757 [doi]
• A True Single-Phase 8-bit Adiabatic MultiplierSuhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou. 758-763 [doi]
• TCG: A Transitive Closure Graph-Based Representation for Non-Slicing FloorplansJai-Ming Lin, Yao-Wen Chang. 764-769 [doi]
• Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block ListYuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu. 770-775 [doi]
• Improved Cut Sequences for Partitioning Based PlacementMehmet Can Yildiz, Patrick H. Madden. 776-779 [doi]
• Timing Driven Placement using Physical Net ConstraintsBill Halpin, C. Y. Roger Chen, Naresh Sehgal. 780-783 [doi]
• From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-ChipLuca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino. 784-789 [doi]
• Panel: What Drives EDA Innovation?Steven E. Schulz, Georgia Marszalek, Greg Hinckley, Greg Spirakis, Karen Vahtra, John A. Darringer, J. George Janac, Handel H. Jones. 790-791 [doi]
• Built-In Self-Test for Signal IntegrityMehrdad Nourani, Amir Attarha. 792-797 [doi]
• Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC InterconnectsKaustav Banerjee, Amit Mehrotra. 798-803 [doi]
• Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-TalkYehia Massoud, Jamil Kawa, Don MacMillen, Jacob White. 804-809 [doi]
• Automated Pipeline DesignDaniel Kroening, Wolfgang J. Paul. 810-815 [doi]
• A New Verification Methodology for Complex Pipeline BehaviorKazuyoshi Kohno, Nobu Matsumoto. 816-821 [doi]
• Pre-silicon Verification of the Alpha 21364 Microprocessor Error Handling SystemRichard Lee, Benjamin Tsien. 822-827 [doi]
• Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage ProcessorsGang Quan, Xiaobo Hu. 828-833 [doi]
• Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-ServiceQinru Qiu, Qing Wu, Massoud Pedram. 834-839 [doi]
• Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded SystemsJinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi. 840-845 [doi]
• Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional IntegrationRongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes. 846-851 [doi]
• Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE ApplicationsSeungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake. 852-857 [doi]
• Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided SearchFrank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich. 858-863 [doi]