Abstract is missing.
- kNN-CAM: A k-Nearest Neighbors-based Configurable Approximate Floating Point MultiplierMing Yan, Yuntao Song, Yiyu Feng, Ghasem Pasandi, Massoud Pedram, Shahin Nazarian. 1-7 [doi]
- Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency ResilienceArman Roohi, Shaahin Angizi, Deliang Fan, Ronald F. DeMara. 8-13 [doi]
- Towards Collaborative Intelligence Friendly Architectures for Deep LearningAmir Erfan Eshratifar, Amirhossein Esmaili, Massoud Pedram. 14-19 [doi]
- A General Framework to Map Neural Networks onto Neuromorphic ProcessorHaowen Fang, Amar Shrestha, Ziyi Zhao, Yanzhi Wang, Qinru Qiu. 20-25 [doi]
- Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping ApproachGhasem Pasandi, Shahin Nazarian, Massoud Pedram. 26-32 [doi]
- Fast Mapping-Based High-Level Synthesis of Pipelined CircuitsChaofan Li, Sachin S. Sapatnekar, Jiang Hu. 33-38 [doi]
- Characterization of Fast, Accurate Leakage Power Models for IEEE P2416Barkha Gupta, W. Rhett Davis. 39-44 [doi]
- Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel ComputingYukio Miyasaka, Ashish Mittal, Masahiro Fujita. 45-51 [doi]
- Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation PlatformMasoud Zabihi, Zhengyang Zhao, D. C. Mahendra, Zamshed I. Chowdhury, Salonik Resch, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar. 52-57 [doi]
- Low Restoration-Energy Differential Spin Hall Effect MRAM for High-Speed Nonvolatile SRAM ApplicationSonal Shreya, Brajesh Kumar Kaushik. 58-63 [doi]
- A Multi-Driver Write Scheme for Reliable and Energy Efficient 1S1R ReRAM Crossbar ArraysSherif Amer, Garrett S. Rose. 64-69 [doi]
- Application of Probabilistic Spin Logic (PSL) in Detecting Satisfiability of a Boolean FunctionVaibhav Agarwal, Sneh Saurabh. 70-75 [doi]
- A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit SimulationXu Liu, Alessandro Bernardini, Ulf Schlichtmann, Xing Zhou. 76-80 [doi]
- An Automated Design Flow for Synthesis of Optimal Switching Power SupplyPradeep Chawda, Anupriya Prasad, Kunjal Rathod, Kritika Solanki. 81-84 [doi]
- Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization AlgorithmsPrateek Gupta, Harshini Mandadapu, Shirisha Gourishetty, Zia Abbas. 85-91 [doi]
- Resilient Reorder Buffer Design for Network-on-ChipZheng Xu, Jacob Abraham. 92-97 [doi]
- Simulation Based Assessment of SRAM Data Retention VoltageZ. Dong, X. Cao, M. Ahosan Ul Karim, V. Joshi, T. Klick, J. Schmid. 98-103 [doi]
- Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable SystemsMohamad Hammam Alsafrjalani, Tosiron Adegbija, Lokesh Ramamoorthi. 104-109 [doi]
- A Scalable Image/Video Processing Platform with Open Source Design and Verification EnvironmentXiaokun Yang, Yunxiang Zhang, Lei Wu. 110-116 [doi]
- Power-aware IoT based Smart Health Monitoring using Wireless Body Area NetworkJitumani Sarma, Akash Katiyar, Rakesh Biswas, Hemanta Kumar Mondal. 117-122 [doi]
- A Comprehensive Evaluation of Power Delivery Schemes for Modern MicroprocessorsJawad Haj-Yahya, Efraim Rotem, Avi Mendelson, Anupam Chattopadhyay. 123-130 [doi]
- State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power EfficiencyKaustav Goswami, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee. 131-137 [doi]
- Deterministic Stochastic Computation Using Parallel DatapathsAlexander J. Groszewski, Travis Lenz. 138-144 [doi]
- MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory ArchitectureJoonseop Sim, Minsu Kim, Yeseong Kim, Saransh Gupta, Behnam Khaleghi, Tajana Rosing. 145-150 [doi]
- Amoeba-Inspired Stochastic Hardware SAT SolverKazuaki Hara, Naoki Takeuchi, Masashi Aono, Yuko Hara-Azumi. 151-156 [doi]
- Accelerating Deterministic Bit-Stream Computing with Resolution SplittingM. Hassan Najafi, S. Rasoul Faraji, Bingzhe Li, David J. Lilja, Kia Bazargan. 157-162 [doi]
- High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAsPrasad B. M. Prabhu, Khyamling Parane, Basavaraj Talawar. 163-169 [doi]
- MReC: A Multilayer Photonic Reservoir Computing ArchitectureDharanidhar Dhang, Syed Ali Hasnain, Rabi Mahapatra. 170-175 [doi]
- Dynamic Reconfiguration of CNNs for Input-Dependent ApproximationMaedeh Hemmat, Azadeh Davoodi. 176-182 [doi]
- An Application Specific Processor Architecture with 3D Integration for Recurrent Neural NetworksSumon Dey, Paul D. Franzon. 183-190 [doi]
- Task-Based Neuromodulation Architecture for Lifelong LearningAnurag Reddy Daram, Dhireesha Kudithipudi, Angel Yanguas-Gil. 191-197 [doi]
- PUF-PassSE: A PUF based Password Strength Enhancer for IoT ApplicationsQian Wang, Mingze Gao, Gang Qu. 198-203 [doi]
- On SAT-Based Attacks On Encrypted Sequential Logic CircuitsYasaswy Kasarabada, Suyuan Chen, Ranga Vemuri. 204-211 [doi]
- A Darwinian Genetic Algorithm for State Encoding Based Finite State Machine WatermarkingMatthew Lewandowski, Srinivas Katkoori. 210-215 [doi]
- Lightweight Secure-Boot Architecture for RISC-V System-on-ChipJawad Haj-Yahya, Ming Ming Wong, Vikramkumar Pudi, Shivam Bhasin, Anupam Chattopadhyay. 216-223 [doi]
- VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum TechnologyAlvin D. Wong, Kevin Su, Hang Sun, Arash Fayyazi, Massoud Pedram, Shahin Nazarian. 224-230 [doi]
- Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power ApplicationsYa-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang. 231-234 [doi]
- Impact of Self-heating on Performance and Reliability in FinFET and GAAFET DesignsVidya A. Chhabria, Sachin S. Sapatnekar. 235-240 [doi]
- Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FETHung-Han Lin, Vita Pi-Ho Hu. 241-246 [doi]
- Behavioral Modeling of Tunable I/O Drivers with Pre-emphasis Using Neural NetworksHuan Yu, Jaemin Shin, Tim Michalka, Mourad Larbi, Madhavan Swaminathan. 247-252 [doi]
- Small Memory Footprint Neural Network AcceleratorsKenshu Seto, Hamid Nejatollahi, Jiyoung An, Sujin Kang, Nikil D. Dutt. 253-258 [doi]
- Minimizing Classification Energy of Binarized Neural Network Inference for Wearable DevicesMorteza Hosseini, Hirenkumar Paneliya, Utteja Kallakuri, Mohit Khatwani, Tinoosh Mohsenin. 259-264 [doi]
- Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural NetworksKatayoun Katayounnneshatpour, Farnaz Behnia, Houman Homayoun, Avesta Sasan. 265-270 [doi]
- Assertion Coverage Aware Trace Signal Selection in Post-Silicon ValidationXiaobang Liu, Ranga Vemuri. 271-277 [doi]
- A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration DebugYuting Cao, Hao Zheng, Sandip Ray. 278-283 [doi]
- Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single FaultsPeikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita. 284-290 [doi]
- Deep Learning-Based Wafer-Map Failure Pattern Recognition FrameworkTsutomu Ishida, Izumi Nitta, Daisuke Fukuda, Yuzi Kanazawa. 291-297 [doi]
- Drive-Strength Selection for Synthesis of Leakage-Dominant CircuitsMahfuzul Islam, Shinichi Nishizawa, Yusuke Matsui, Yoshinobu Ichida. 298-303 [doi]
- Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation ToolsBilly Huggins, W. Rhett Davis, Paul D. Franzon. 304-310 [doi]
- An Artificial Intelligence Approach to EDA Software Testing: Application to Net Delay Algorithms in FPGAsMadhu Raman, Nizar Abdallah, Julien Dunoyer. 311-316 [doi]
- Impact of Double-Row Height Standard Cells on Placement and RoutingRung-Bin Lin, Yu-Xiang Chiang. 317-322 [doi]
- A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC DesignShantonu Das, Dae-Hyun Kim. 323-328 [doi]
- Routing Complexity Minimization of Monolithic Three-Dimensional Integrated CircuitsSheng-En David Lin, Dae-Hyun Kim. 329-334 [doi]
- Towards Energy Efficient non-von Neumann Architectures for Deep LearningAntara Ganguly, Rajeev Muralidhar, Virendra Singh. 335-342 [doi]
- Closing the Verification Gap with Static Sign-offPranav Ashar, Vinod Viswanath. 343-347 [doi]