Basavaraj Talawar - researchr alias

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Viewing Publication 1 - 35 from 35

2026

Ultra-Fast and Accurate Estimation of Large-Scale and Multi-Level Mesh-Based On-Chip Architectures Using Machine Learning and MultiprocessingAnil Kumar, Basavaraj Talawar, S. Mahadevi. access, 14:21542-21552, 2026. [doi]

2024

2022

Knowledgeable network-on-chip accelerator for fast and accurate simulations using supervised learning algorithms and multiprocessingAnil Kumar, Basavaraj Talawar. ijiei, 10(2):160-182, 2022. [doi]

LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area for Network-On-Chip ArchitecturesAnil Kumar, Basavaraj Talawar. jcsc, 31(11), 2022. [doi]

2021

FPGA friendly NoC simulation acceleration framework employing the hard blocksPrabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar. computing, 103(8):1791-1813, 2021. [doi]

Parallel deterministic local search heuristic for minimum latency problemPramod Yelmewad, Basavaraj Talawar. cluster, 24(2):969-995, 2021. [doi]

Parallel Version of Local Search Heuristic Algorithm to Solve Capacitated Vehicle Routing ProblemPramod Yelmewad, Basavaraj Talawar. cluster, 24(4):3671-3692, 2021. [doi]

2020

Power and performance analysis of 3D network-on-chip architecturesBheemappa Halavar, Basavaraj Talawar. cee, 83:106592, 2020. [doi]

ELBA-NoC: ensemble learning-based accelerator for 2D and 3D network-on-chip architecturesAnil Kumar, Basavaraj Talawar. ijcse, 23(4):319-335, 2020. [doi]

LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGAKhyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar. todaes, 25(1), 2020. [doi]

P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGAKhyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar. wpc, 114(4):3295-3319, 2020. [doi]

An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard BlocksPrabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar. cssp, 39(10):5247-5271, 2020. [doi]

PowerDPDK: Software-Based Real-Time Power Measurement for DPDK ApplicationsMishal Shah, Mehnaz Yunus, Pavan Vachhani, Leslie Monis, Mohit P. Tahiliani, Basavaraj Talawar. nfvsdn 2020: 13-18 [doi]

2019

Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architecturesBheemappa Halavar, Ujjwal Pasupulety, Basavaraj Talawar. simpra, 96, 2019. [doi]

YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAsKhyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar. jcsc, 28(12):1950202, 2019. [doi]

Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGAKhyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar. vlsi-dat 2019: 1-4 [doi]

High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAsPrasad B. M. Prabhu, Khyamling Parane, Basavaraj Talawar. isqed 2019: 163-169 [doi]

Analysis of cache behaviour and software optimizations for faster on-chip network simulationsPrabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar. saem, 10(4):696-712, 2019. [doi]

High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 BlocksPrabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar. vlsi-dat 2019: 1-4 [doi]

Parallel iterative hill climbing algorithm to solve TSP on GPUPramod Yelmewad, Basavaraj Talawar. concurrency, 31(7), 2019. [doi]

MMAS on GPU for Large TSP InstancesPramod Yelmewad, Aniket Kumar, Basavaraj Talawar. icccnt 2019: 1-6 [doi]

2018

Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-ChipBheemappa Halavar, Basavaraj Talawar. spcom 2018: 282-286 [doi]

OP3DBFT: A Power and Performance Optimal 3D BFT NoC ArchitectureBheemappa Halavar, Basavaraj Talawar. isda 2020: 923-933 [doi]

Machine Learning Based Framework to Predict Performance Evaluation of On-Chip NetworksAnil Kumar, Basavaraj Talawar. ic3 2018: 1-6 [doi]

YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAsKhyamling Parane, Basavaraj Talawar, Prabhu Prasad B. M.. vlsid 2018: 67-72 [doi]

Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) ArchitecturesUjjwal Pasupulety, Bheemappa Halavar, Basavaraj Talawar. ised 2018: 236-240 [doi]

Accurate Power and Latency Analysis of a Through-Silicon Via(TSV)Ujjwal Pasupulety, Bheemappa Halavar, Basavaraj Talawar. icacci 2018: 688-694 [doi]

Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGAG. S. Sangeetha, Vignesh Radhakrishnan, Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar. ised 2018: 129-134 [doi]

2017

GPU-Based Iterative Hill Climbing Algorithm to Solve Symmetric Traveling Salesman ProblemBasavaraj Talawar, Pramod Yelmewad. tophpc 2018: 221-241 [doi]

GPU implementation of non-local maximum likelihood estimation method for denoising magnetic resonance imagesAdithya H. K. Upadhya, Basavaraj Talawar, Jeny Rajan. jrtip, 13(1):181-192, 2017. [doi]

2016

Cache analysis and software optimizations for faster on-chip network simulationsKhyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar. iciis 2016: 83-88 [doi]

2015

A Crossbar Interconnection Network in DNABasavaraj Talawar. ipps 2015: 342-345 [doi]

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Publications by 'Basavaraj Talawar'

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2026

2024

2022

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2020

2019

2018

2017

2016

2015

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