Abstract is missing.
- Electrical modeling and analysis of 3D synaptic array using vertical RRAM structureHongyu An, M. Amimul Ehsan, Zhen Zhou, Yang Yi 0002. 1-6 [doi]
- SRAM voltage scaling for energy-efficient convolutional neural networksLita Yang, Boris Murmann. 7-12 [doi]
- Stochastic-based multi-stage streaming realization of deep convolutional neural networkMohammed Alawad, Mingjie Lin. 13-18 [doi]
- A fast and ultra low power time-based spiking neuromorphic architecture for embedded applicationsTao Liu, Wujie Wen. 19-22 [doi]
- Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computingWei-Hao Chen, Win-San Khwa, Jun-Yi Li, Wei-Yu Lin, Huan-Ting Lin, Yongpan Liu, Yu Wang 0002, Huaqiang Wu, Huazhong Yang, Meng-Fan Chang. 23-28 [doi]
- Harnessing ferroelectrics for non-volatile memories and logicSumeet Kumar Gupta, Danni Wang, Sumitha George, Ahmedullah Aziz, Xueqing Li, Suman Datta, Vijaykrishnan Narayanan. 29-34 [doi]
- Test challenges in embedded STT-MRAM arraysInsik Yoon, Arijit Raychowdhury. 35-38 [doi]
- Evaluating tradeoffs in granularity and overheads in supporting nonvolatile execution semanticsKaisheng Ma, Minli Julie Liao, Xueqing Li, Zhixuan Huan, Jack Sampson. 39-44 [doi]
- Communication limits of on-chip graphene plasmonic interconnectsShaloo Rakheja. 45-51 [doi]
- Variation-immune resistive Non-Volatile Memory using self-organized sub-bank circuit designsNavid Khoshavi, Soheil Salehi, Ronald F. DeMara. 52-57 [doi]
- Constructing fast and energy efficient 1TnR based ReRAM crossbar memoryLei Zhao, Lei Jiang 0001, Youtao Zhang, Nong Xiao, Jun Yang 0002. 58-64 [doi]
- Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementationsXin Fan, Jan Stuijt, Rui Wang, Bo Liu, Tobias Gemmeke. 65-70 [doi]
- Tunnel FET based ultra-low-leakage compact 2T1C SRAMNavneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel. 71-75 [doi]
- Low redundancy matrix-based codes for adjacent error correction with parity sharingShanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, Zhigang Mao. 76-80 [doi]
- 0.6 V operation, 16 % faster set/reset ReRAM boost converter with adaptive buffer voltage for ReRAM and NAND flash hybrid solid-state drivesKota Tsurumi, Masahiro Tanaka, Ken Takeuchi. 81-86 [doi]
- Low temperature endurance failures on flash memoryStephen Heinrich-Barna, Clyde Dunn, Doug Verret. 87-92 [doi]
- Virtual characterization for exhaustive DFM evaluation of logic cell librariesSamuel Pagliarini, Mayler G. A. Martins, Lawrence T. Pileggi. 93-98 [doi]
- Overview and development of EDA tools for integration of DSA into patterning solutionsJ. Andres Torres, Germain Fenger, Daman Khaira, Yuansheng Ma, Yuri Granik, Chris Kapral, Joydeep Mitra, Polina Krasnova, Dehia Ait-Ferhat. 99-103 [doi]
- Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodesKwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang. 104-110 [doi]
- A technique to construct global routing trees for graphene nanoribbon (GNR)Subrata Das, Debesh Kumar Das. 111-118 [doi]
- Regularized logistic regression for fast importance sampling based SRAM yield analysisLama Shaer, Rouwaida Kanj, Rajiv V. Joshi, Maria Malik, Ali Chehab. 119-124 [doi]
- Binary adder circuit design using emerging MIGFET devicesJeferson José Baqueta, Felipe S. Marranghello, Vinicius Neves Possani, Augusto Neutzling, André Inácio Reis, Renato P. Ribas. 125-130 [doi]
- A case for standard-cell based RAMs in highly-ported superscalar processor structuresSungkwan Ku, Elliott Forbes, Rangeen Basu Roy Chowdhury, Eric Rotenberg. 131-137 [doi]
- Energy efficient analog spiking temporal encoder with verification and recovery scheme for neuromorphic computing systemsChenyuan Zhao, Jialing Li, Hongyu An, Yang Yi 0002. 138-143 [doi]
- 3D-NOCET: A tool for implementing 3D-NoCs based on the Direct-Elevator algorithmMaha Beheiry, Hassan Mostafa, Yehea Ismail, Ahmed M. Soliman. 144-148 [doi]
- Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kitVinay Vashishtha, Ankita Dosi, Lovish Masand, Lawrence T. Clark. 149-154 [doi]
- Investigation of magnetic field attacks on commercial Magneto-Resistive Random Access MemoryAlexander Holst, Jae-Won Jang, Swaroop Ghosh. 155-160 [doi]
- A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applicationsChunhua Qi, Liyi Xiao, Mingxue Huo, Tianqi Wang, Rongsheng Zhang, Xuebing Cao. 161-165 [doi]
- A new approach for selecting inputs of logic functions during debugAmir Masoud Gharehbaghi, Masahiro Fujita. 166-173 [doi]
- Fast and energy-aware resource provisioning and task scheduling for cloud systemsHongjia Li, Ji Li, Wang Yao, Shahin Nazarian, Xue Lin, Yanzhi Wang. 174-179 [doi]
- Evaluating the benefits of relaxed BEOL pitch for deeply scaled ICsMehmet Meric Isgenc, Samuel Pagliarini, Renzhi Liu, Larry T. Pileggi. 180-185 [doi]
- STA compatible backend design flow for TSV-based 3-D ICsHarry Kalargaris, Yi-Chung Chen, Vasilis F. Pavlidis. 186-190 [doi]
- Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoderSungyoul Seo, Hyeonchan Lim, Soyeon Kang, Sungho Kang. 191-195 [doi]
- Determining proximal geolocation of IoT edge devices via covert channelMd. Nazmul Islam, Vinay C. Patil, Sandip Kundu. 196-202 [doi]
- Clock tree optimization through selective airgap insertionDaijoon Hyun, Wachirawit Ponghiran, Youngsoo Shin. 203-208 [doi]
- An analytical model for interdependent setup/hold-time characterization of flip-flopsHadi Ahmadi Balef, Hailong Jiao, José Pineda de Gyvez, Kees Goossens. 209-214 [doi]
- High sigma statistical hold time analysis in FinFET sequential circuitsSam C. Lo, Taylor T. Lee, Aaron J. Barker. 215-220 [doi]
- Power prediction of embedded scalar and vector processor: Challenges and solutionsVijay Kiran Kalyanam, Peter G. Sassone, Jacob A. Abraham. 221-228 [doi]
- Power-delay product based resource library construction for effective power optimization in HLSShantanu Dutt, Ouwen Shi. 229-236 [doi]
- Crossover Ring Oscillator PUFZihan Pang, Jiliang Zhang, Qiang Zhou, Shuqian Gong, Xu Qian, Bin Tang. 237-243 [doi]
- Integrated circuit identification and true random numbers using 1.5-transistor flash memoryLawrence T. Clark, James Adams, Keith E. Holbert. 244-249 [doi]
- Methodologies to exploit ATPG tools for de-camouflagingDeepakreddy Vontela, Swaroop Ghosh. 250-256 [doi]
- Low-overhead implementation of logic encryption using gate replacement techniquesXiaoming Chen, Qiaoyi Liu, Yu Wang 0002, Qiang Xu, Huazhong Yang. 257-263 [doi]
- Scan chain based IP fingerprint and identificationXi Chen, Gang Qu, Aijiao Cui, Carson Dunbar. 264-270 [doi]
- Performance-thermal trade-offs for a VFI-enabled 3D NoC architectureDongJin Lee, Sourav Das, Partha Pratim Pande. 271-276 [doi]
- A legalization algorithm for multi-tier gate-level monolithic three-dimensional integrated circuitsYiting Chen, Dae-Hyun Kim. 277-282 [doi]
- Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICsKaoru Furumi, Masashi Imai, Atsushi Kurokawa. 283-288 [doi]
- High performance virtual channel based fully adaptive thermal-aware routing for 3D NoCXin Jiang, Xiangyang Lei, Lian Zeng, Takahiro Watanabe. 289-295 [doi]
- Data interface buffer compensation scheme for fast calibrationSameer Shekhar, Amit K. Jain, Pooja Nukala. 296-300 [doi]
- Chosen-input side-channel analysis on unrolled light-weight cryptographic hardwareVille Yli-Mäyry, Naofumi Homma, Takafumi Aoki. 301-306 [doi]
- An electromagnetic fault injection sensor using Hogge phase-detectorJakub Breier, Shivam Bhasin, Wei He. 307-312 [doi]
- FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliabilitySiarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang. 313-318 [doi]
- Towards lightweight Identity-Based Encryption for the post-quantum-secure Internet of ThingsTim Güneysu, Tobias Oder. 319-324 [doi]
- SHA-3 implementation using ReRAM based in-memory computing architectureDebjyoti Bhattacharjee, Vikramkumar Pudi, Anupam Chattopadhyay. 325-330 [doi]
- A hybrid RFID and CV system for item-level localization of stationary objectsEverton L. Berz, Deivid A. Tesch, Fabiano Passuelo Hessel. 331-336 [doi]
- Energy efficient biopotential acquisition unit for wearable health monitoring applicationsWazir Singh, Yatharth Gupta, Paritosh Jivani, Sujay Deb. 337-341 [doi]
- Wireless charge recovery system for implanted electroencephalography applications in miceLeo Filippini, Diane Lim, Lunal Khuon, Baris Taskin. 342-345 [doi]
- CAP: Configurable resistive associative processor for near-data computingMohsen Imani, Tajana Rosing. 346-352 [doi]
- Performance evaluation of copper and graphene nanoribbons in 2-D NoC structuresRuturaj Pujari, Shaloo Rakheja. 353-359 [doi]
- Processor/memory Co-Scheduling using periodic resource server for real-time systems under peak temperature constraintsGustavo A. Chaparro-Baquero, Shi Sha, Soamar Homsi, Wujie Wen, Gang Quan. 360-366 [doi]
- Data center power management for regulation service using neural network-based power predictionNing Liu, Xue Lin, Yanzhi Wang. 367-372 [doi]
- An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessorsPooneh Safayenikoo, Arghavan Asad, Mahmood Fathy, Farah Mohammadi. 373-378 [doi]
- Workload-aware ASIC flow for lifetime improvement of multi-core IoT processorsScott Lerner, Baris Taskin. 379-384 [doi]
- Post-fabrication calibration of Near-Threshold circuits for energy efficiencyMohammad Saber Golanbari, Saman Kiamehr, Fabian Oboril, Anteneh Gebregiorgis, Mehdi Baradaran Tahoori. 385-390 [doi]
- Composite spintronic accuracy-configurable adder for low power Digital Signal ProcessingShaahin Angizi, Zhezhi He, Ronald F. DeMara, Deliang Fan. 391-396 [doi]
- Low latency divider using ensemble of moving average curvesYuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura. 397-402 [doi]
- Adder implementation in reconfigurable resistive switching crossbarPravin Mane, Sudeep Mishra, Ravish Deliwala, C. K. Ramesha. 403-408 [doi]
- High precision yet wide range on-chip oscillator with dual charge-discharge techniqueAbhijit Das, Joonsung Park. 409-412 [doi]
- In&Out: Restructuring for threshold logic network optimizationChia-Chun Lin, Chiao-Wei Huang, Chun-Yao Wang, Yung-Chih Chen. 413-418 [doi]
- Systematic approximate logic optimization using don't care conditionsSahand Salamat, Mehrnaz Ahmadi, Bijan Alizadeh, Masahiro Fujita. 419-425 [doi]
- Comparative study of path selection and objective function in replacing NBTI mitigation logicShumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato. 426-431 [doi]
- Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designsQinhao Wang, Yusuke Kimura, Masahiro Fujita. 432-437 [doi]
- Cost-quality trade-offs of approximate memory repair mechanisms for image dataQianqian Fan, Sachin S. Sapatnekar, David J. Lilja. 438-444 [doi]
- Aging-aware critical paths for process related validation in the presence of NBTIPhaninder Alladi, Spyros Tragoudas. 445-448 [doi]
- Broadcast scan compression based on deterministic pattern generation algorithmHyeonchan Lim, Sungyoul Seo, Soyeon Kang, Sungho Kang. 449-453 [doi]
- Wordline overdriving test: An effective predictive testing method for SRAMs against BTI agingJizhe Zhang, Sandeep K. Gupta. 454-459 [doi]
- Failures and verification solutions related to untimed paths in SOCsPranav Ashar, Vikas Sachdeva, Vinod Viswanath. 460-465 [doi]