FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability

Siarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang. FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability. In 18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, CA, USA, March 14-15, 2017. pages 313-318, IEEE, 2017. [doi]

Abstract

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