An efficient automatic test generation system for path delay faults in combinational circuits

Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal. An efficient automatic test generation system for path delay faults in combinational circuits. In 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India. pages 161-165, IEEE Computer Society, 1995. [doi]

Abstract

Abstract is missing.