PAR-APLAC: Parallel Circuit Analysis and Optimization

Eero Pajarre, Tapani Ritoniemi, T. Tenhunen. PAR-APLAC: Parallel Circuit Analysis and Optimization. In Gerald Musgrave, editor, Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992. pages 584-589, IEEE Computer Society Press, 1992. [doi]

Abstract

Abstract is missing.