Clay S. Gloster Jr. - researchr alias

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Viewing Publication 1 - 15 from 15

2017

Smart City Service Acceleration on FPGAsYoungsoo Kim, Marcus Garcia, Alan Chen, Nathan Wong, Shrikant Jadhav, Clay S. Gloster Jr.. bigdataservice 2017: 243-248 [doi]

Improving the Accuracy of Arctan for Face DetectionYoungsoo Kim, Hossein Shahdoost, Shrikant Jadhav, Clay S. Gloster Jr.. fccm 2017: 202 [doi]

2016

Project based courses in control cyber physical system co-designYoungsoo Kim, Alan Chen, Shrikant Jadhav, Clay S. Gloster Jr., Thuy Le, Ping Hsu. esweek 2016: [doi]

Dataflow to Hardware Synthesis Framework on FPGAsYoungsoo Kim, Shrikant Jadhav, Clay S. Gloster Jr.. sbac-pad 2016: 91-96 [doi]

2015

An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only)Michaela E. Amoo, Youngsoo Kim, Vance Alford, Shrikant Jadhav, Naser I. El-Bathy, Clay S. Gloster Jr.. fpga 2015: 263 [doi]

Acceleration of Synthetic Aperture Radar (SAR) Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only)Youngsoo Kim, William Harding, Clay S. Gloster Jr., Winser E. Alexander. fpga 2015: 271 [doi]

2014

Intelligent surveillance lifecycle architecture for epidemiological data clustering using Twitter and novel genetic algorithmNaser El-Bathy, Clay S. Gloster Jr., Ghassan Azar, Mohammed El-Bathy, Gordon Stein, Ricky Stevenson. eit 2014: 149-155 [doi]

2009

IRCDB: A Database of Inter-residues Contacts in Protein ChainsPeng Chen, Chunmei Liu, Legand L. Burge III, Mahmood Mohammad, William M. Southerland, Clay S. Gloster Jr., Bing Wang. dbkda 2009: 1-6 [doi]

2007

A Configurable Processor Synthesis SystemWanda Gay, Clay S. Gloster Jr.. fccm 2007: 331-332 [doi]

2000

Parallel image processin gwith the block data paralel architectureWinser E. Alexander, Douglas S. Reeves, Clay S. Gloster Jr.. ibmrd, 44(5):681-702, 2000. [doi]

Implementation of Multispectral Image Classification on a Remote Adaptive ComputerMarco A. Figueiredo, Clay S. Gloster Jr., Mark A. Stephens, Corey A. Graves, Mouna Nakkar. vlsi, 2000(3):307-319, 2000. [doi]

1996

Parallel image processing with the block data parallel architectureWinser E. Alexander, Douglas S. Reeves, Clay S. Gloster Jr.. pieee, 84(7):947-968, 1996. [doi]

1992

Cellular scan test generation for sequential circuitsClay S. Gloster Jr., Franc Brglez. eurodac 1992: 530-536 [doi]

1990

Built-in self-test with weighted random pattern hardwareFranc Brglez, Clay S. Gloster Jr., Gershon Kedem. iccd 1990: 161-166 [doi]

1989

Boundary scan with built-in self-testClay S. Gloster Jr., Franc Brglez. dt, 6(1):36-44, 1989. [doi]

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