Abstract is missing.
- High-Performance Hardware Merge SorterSusumu Mashimo, Thiem Van Chu, Kenji Kise. 1-8 [doi]
- Communication-Aware MCMC Method for Big Data Applications on FPGAsShuanglong Liu, Christos-Savvas Bouganis. 9-16 [doi]
- Terabyte Sort on FPGA-Accelerated Flash StorageSang-Woo Jun, Shuotao Xu, Arvind. 17-24 [doi]
- Improved Synthesis of Compressor Trees on FPGAs in High-Level SynthesisLe Tu, Yuelai Yuan, Kan Huang, Xiaoqiang Zhang, Zixin Wang, Dihu Chen. 25 [doi]
- SWiF: A Simplified Workload-Centric Framework for FPGA-Based ComputingDavid Ojika, Piotr Majcher, Wojciech Neubauer, Suchit Subhaschandra, Darin Acosta. 26 [doi]
- Megrez: Parallelizing FPGA Routing with Strictly-Ordered PartitioningMinghua Shen, Guojie Luo. 27 [doi]
- An FPGA Design Framework for CNN Sparsification and AccelerationSicheng Li, Wei Wen, Yu Wang, Song Han, Yiran Chen, Hai Li. 28 [doi]
- FPGA Delay Model Considering Logic-Level and Transistor-Level ParametersQiang Liu, HanJing Qian. 29 [doi]
- Scheduling Considerations for Voter Checking in TMR-MER SystemsNguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel. 30 [doi]
- Bit-Width Based Resource Partitioning for CNN Acceleration on FPGAJianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei. 31 [doi]
- On Bit-Serial NoCs for FPGAsNachiket Kapre. 32-39 [doi]
- Implementing FPGA Overlay NoCs Using the Xilinx UltraScale Memory CascadesNachiket Kapre. 40-47 [doi]
- Efficient GPGPU Computing with Cross-Core Resource Sharing and Core ReconfigurationAshutosh Dhar, Deming Chen. 48-55 [doi]
- An Architecture for the Acceleration of a Hybrid Leaky Integrate and Fire SNN on the Convey HC-2ex FPGA-Based ProcessorEmmanouil Kousanakis, Apostolos Dollas, Euripides Sotiriades, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Athanasia Papoutsi, Panagiotis C. Petrantonakis, Panayiota Poirazi, Spyridon Chavlis, George Kastellakis. 56-63 [doi]
- FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron ColliderEdward Bartz, Jorge Chaves, Yuri Gershtein, Eva Halkiadakis, Michael Hildreth, Savvas Kyriacou, Kevin Lannon, Anthony Lefeld, Anders Ryd, Louise Skinnari, Robert Stone, Charles Strohman, Zhengcheng Tao, Brian Winer, Peter Wittich, Zhiru Zhang, Margaret Zientek. 64-71 [doi]
- Bonded Force Computations on FPGAsQingqing Xiong, Martin C. Herbordt. 72-75 [doi]
- Efficient Particle-Grid Space Interpolation of an FPGA-Accelerated Particle-in-Cell Plasma SimulationAlmomany Abedalmuhdi, B. Earl Wells, Ken-ichi Nishikawa. 76-79 [doi]
- A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and OperatorsYohann Uguen, Florent de Dinechin, Steven Derrien. 80 [doi]
- A Case for Common-Case: On FPGA Acceleration of Erasure CodingReza Nakhjavani, Jianwen Zhu. 81 [doi]
- Accelerating Large-Scale Graph Analytics with FPGA and HMCSoroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li. 82 [doi]
- Fast and Energy-Driven Design Space Exploration for Heterogeneous ArchitecturesBaptiste Roux, Matthieu Gautier, Olivier Sentieys, Jean-Philippe Delahaye. 83 [doi]
- A Parameterizable Activation Function Generator for FPGA-Based Neural Network ApplicationsSam M. H. Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang, Hayden Kwok-Hay So. 84 [doi]
- Customizing Neural Networks for Efficient FPGA ImplementationMohammad Samragh, Mohammad GhasemZadeh, Farinaz Koushanfar. 85-92 [doi]
- Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip TransferYongming Shen, Michael Ferdman, Peter A. Milder. 93-100 [doi]
- Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAsLiqiang Lu, Yun Liang, Qingcheng Xiao, Shengen Yan. 101-108 [doi]
- Using Runahead Execution to Hide Memory Latency in High Level SynthesisShane T. Fleming, David B. Thomas. 109-116 [doi]
- Energy Efficient Loop Unrolling for Low-Cost FPGAsNaveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier. 117-120 [doi]
- Evaluating Rapid Application Development with Python for Heterogeneous Processor-Based FPGAsAndrew G. Schmidt, Gabriel Weisz, Matthew French. 121-124 [doi]
- HLScope: High-Level Performance Debugging for FPGA DesignsYoung Kyu Choi, Jason Cong. 125-128 [doi]
- TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLSGanghee Lee, Dimitris Agiakatsikas, Tong Wu, Ediz Cetin, Oliver Diessel. 129-132 [doi]
- Exploration of FPGA-Based Packet Switches for Rack-Scale Computers on a BoardJong Hun Han, Neelakandan Manihatty Bojan, Andrew W. Moore 0002. 133 [doi]
- An Out-of-Order Load-Store Queue for Spatial ComputingLana Josipovic, Philip Brisk, Paolo Ienne. 134 [doi]
- Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGAPhilip Colangelo, Randy Huang, Enno Lübbers, Martin Margala, Kevin Nealis. 135 [doi]
- Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage DevicesJeffrey Goeders. 136-143 [doi]
- The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for SimulationJohn Mawer, Oscar Palomar, Cosmin Gorgovan, Andy Nisbet, Will Toms, Mikel Luján. 144-151 [doi]
- FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid TemplatesYijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong. 152-159 [doi]
- FPGA-Accelerated Dense Linear Machine Learning: A Precision-Convergence Trade-OffKaan Kara, Dan Alistarh, Gustavo Alonso, Onur Mutlu, Ce Zhang. 160-167 [doi]
- A Configurable FPGA Implementation of the Tanh Function Using DCT InterpolationAhmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet. 168-171 [doi]
- ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path EncodingChin Hau Hoo, Akash Kumar 0001. 172-179 [doi]
- Automata-to-Routing: An Open-Source Toolchain for Design-Space Exploration of Spatial Automata Processing ArchitecturesJack Wadden, Samira Khan, Kevin Skadron. 180-187 [doi]
- Relocating Encrypted Partial Bitstreams by Advance Task Address LoadingAdewale Adetomi, Godwin Enemali, Tughrul Arslan. 188-191 [doi]
- CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA ComputingHoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima. 192 [doi]
- Multi-FPGA Evaluation Platform for Disaggregated ComputingDimitris Theodoropoulos, Nikolaos Alachiotis, Dionisios N. Pnevmatikatos. 193 [doi]
- Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAsFubing Mao, Wei Zhang, Bingsheng He, SiewKei Lam. 194 [doi]
- Exploring High Efficiency Hardware Accelerator for the Key Algorithm of Square Kilometer Array Telescope Data ProcessingQian Wu, Yongxin Zhu, Xu Wang, Mengjun Li, Junjie Hou, Ali Masoumi. 195 [doi]
- Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA PlatformsRaghid Morcel, Haitham Akkary, Hazem M. Hajj, Mazen A. R. Saghir, Anil Keshavamurthy, Rahul Khanna, Hassan Artail. 196 [doi]
- A Network-on-Chip Based H.264 Video Decoder Prototype Implemented on FPGAsIan J. Barge, Cristinel Ababei. 197 [doi]
- Applying the Flask Security Architecture to Secure SoC DesignFestus Hategekimana, Christophe Bobda. 198 [doi]
- A Real-Time Embedded FPGA Processor for a Stand-Alone Dual-Mode Assistive DeviceAli Jafari, Maysam Ghovanloo, Tinoosh Mohsenin. 199 [doi]
- CAPSL: A Tool for Automatic Generation of Hardware Sandboxes for IP SecurityTaylor J. L. Whitaker, Christophe Bobda. 200 [doi]
- A Scalable FPGA-Based Accelerator for High-Throughput MCMC AlgorithmsMorteza Hosseini, Rashidul Islam, Amey M. Kulkarni, Tinoosh Mohsenin. 201 [doi]
- Improving the Accuracy of Arctan for Face DetectionYoungsoo Kim, Hossein Shahdoost, Shrikant Jadhav, Clay S. Gloster Jr.. 202 [doi]
- K-Mer Counting Using Bloom Filters with an FPGA-Attached HMCNathaniel McVicar, Chih-Ching Lin, Scott Hauck. 203-210 [doi]
- Centaur: A Framework for Hybrid CPU-FPGA DatabasesMuhsen Owaida, David Sidler, Kaan Kara, Gustavo Alonso. 211-218 [doi]
- Scalable Network Function Virtualization for Heterogeneous MiddleboxesXuzhi Zhang, Xiaozhe Shao, George Provelengios, Naveen Kumar Dumpala, Lixin Gao, Russell Tessier. 219-226 [doi]
- A Nanosecond-Level Hybrid Table Design for Financial Market Data GeneratorsHaohuan Fu, Conghui He, Wayne Luk, Weijia Li, Guangwen Yang. 227-234 [doi]