Abstract is missing.
- Transient Fault Tolerant QDI Interconnects Using Redundant Check CodeGuangda Zhang, Wei Song 0002, Jim D. Garside, Javier Navaridas, Zhiying Wang. 3-10 [doi]
- Global Interconnect and Control Synthesis in System Level Architectural Synthesis FrameworkShuo Li, Ahmed Hemani. 11-17 [doi]
- Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoCShaoteng Liu, Axel Jantsch, Zhonghai Lu. 21-28 [doi]
- Parallel Deadlock Detection and Recovery for Networks-on-Chip Dedicated to Diffused ComputationsPierre Bomel, Marc Sevaux. 29-36 [doi]
- Run-Time Slack Distribution for Real-Time Data-Flow Applications on Embedded MPSoCPavel G. Zaykov, Georgi Kuzmanov, Anca Mariana Molnos, Kees Goossens. 39-47 [doi]
- Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPsPablo Abad, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio. 48-55 [doi]
- Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip MultiprocessorsSandro Bartolini, Luca Lusnig, Enrico Martinelli. 56-59 [doi]
- Non-intrusive NoC DFS for Soft Real-Time Multimedia ApplicationsMiltos D. Grammatikakis, Antonis Papagrigoriou, Polydoros Petrakis, George Kornaros. 60-63 [doi]
- Early Performance Evaluation of Multi-OS Embedded Platforms Using Native SimulationRodrigo Fernández, Hector Posadas, Eugenio Villar. 64-67 [doi]
- Impact of 3D IC on NoC Topologies: A Wire Delay ConsiderationMohamad Hairol Jabbar, Dominique Houzet, Omar Hammami. 68-72 [doi]
- High Performance Bitwise OR Based Submesh Allocation for 2D Mesh-Connected CMPsLuka B. Daoud, Victor Goulart. 73-77 [doi]
- A General Framework for Average-Case Performance Analysis of Shared ResourcesSahar Foroutan, Benny Akesson, Kees Goossens, Frédéric Pétrot. 78-85 [doi]
- A Static Analysis Approach for Verification of Synchronization Correctness of SystemC DesignsMikhail Glukhikh, Mikhail J. Moiseev, Sergey I. Salishev. 89-96 [doi]
- Calibration Error Bound Estimation in Performance ModelingVidya V. Parappurath, Jeroen Voeten, Kees C. Kotterink. 97-102 [doi]
- pCache: An Observable L1 Data Cache Model for FPGA Prototyping of Embedded SystemsParthasarathy Ravishankar, Samar Abdi. 103-110 [doi]
- Generation of Structural VHDL Code with Library Components from Formal Event-B ModelsSergey Ostroumov, Leonidas Tsiopoulos, Kaisa Sere, Juha Plosila. 111-118 [doi]
- Digital Late-Transition Metastability Simulation ModelThomas Polzer, Andreas Steininger. 121-128 [doi]
- Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and LogarithmsAlexander Uhl, Juergen Becker. 129-135 [doi]
- Identifying NBTI-Critical Paths in Nanoscale LogicRaimund Ubar, Fabian Vargas, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Letícia Maria Bolzani Poehls. 136-141 [doi]
- Efficient Construction of Global Time in SoCs Despite Arbitrary FaultsChristoph Lenzen, Matthias Függer, Markus Hofstatter, Ulrich Schmid. 142-151 [doi]
- Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo DecoderVianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet. 155-162 [doi]
- A Flexible Radio Transmitter for TVWS Based on FBMCVincent Berg, Jean-Baptiste Dore, Dominique Noguet. 163-167 [doi]
- A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case StudyCarlo Condo, Amer Baghdadi, Guido Masera. 168-174 [doi]
- A Testbed for Evaluating LTE in High-Speed TrainsJosé Rodríguez-Piñeiro, José Antonio García-Naya, Angel Carro-Lagoa, Luis Castedo. 175-182 [doi]
- Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAsHasan Erdem Yantir, Salih Bayar, Arda Yurdakul. 185-192 [doi]
- Dynamic Noise Estimation Approach for X-Ray Detectors on FPGAsFlorian Aschauer, Walter Stechele, Johannes Treis. 193-200 [doi]
- A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource ConstraintsAdrien Prost-Boucle, Olivier Muller, Frederic Rousseau. 201-208 [doi]
- An Efficient Hardware Implementation of a SAT Problem Solver on FPGATeodor Ivan, El Mostapha Aboulhamid. 209-216 [doi]
- Software Modification Aided Transient Error Tolerance for Embedded SystemsRishad A. Shafik, Gerard K. Rauwerda, Jordy Potman, Kim Sunesen, Dhiraj K. Pradhan, Jimson Mathew, Ioannis Sourdis. 219-226 [doi]
- Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant AreaLukas Miculka, Martin Straka, Zdenek Kotásek. 227-234 [doi]
- Virtual TMR Schemes Combining Fault Tolerance and Self RepairTobias Koal, Markus Ulbricht, Heinrich Theodor Vierhaus. 235-242 [doi]
- Data Flow Analysis of Software Executed by Unreliable HardwarePeter Raab, Stanislav Racek, Stefan Kramer, Jürgen Mottok. 243-249 [doi]
- SMAC: Smart Systems Co-designNicola Bombieri, Giuliana Drogoudis, Giuliana Gangemi, R. Gillon, Enrico Macii, Massimo Poncino, Salvatore Rinaudo, Francesco Stefanni, D. Trachanis, M. van Helvoort. 253-259 [doi]
- MultiPARTES: Multicore Virtualization for Mixed-Criticality SystemsSalvador Trujillo, Alfons Crespo, Alejandro Alonso. 260-265 [doi]
- E2LP: A Unified Embedded Engineering Learning PlatformMiodrag Temerinac, Ivan Kastelan, Karolj Skala, Branka Medved Rogina, Leonhard Reindl, Florent Souvestre, Margarita Anastassova, Roman Szewczyk, Jan Piwinski, Jorge R. Lopez Benito, Enara Artetxe Gonzalez, Nikola Teslic, Vlado Sruk, Moshe Barak. 266-271 [doi]
- The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation TeradevicesMarco Solinas, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Feng Li, Mikel Luján, Laurent Morin, Avi Mendelson, Nacho Navarro, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Mateo Valero, Sebastian Weis, Ian Watson, Stéphane Zuckerman, Roberto Giorgi. 272-279 [doi]
- Novel Dynamic Gate Topology for Superpipelines in DSM TechnologiesJuan Núñez, Maria J. Avedillo, José M. Quintana. 280-283 [doi]
- Comparison of FPGA and ASIC Implementation of a Linear Congruence SolverJiri Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický. 284-287 [doi]
- VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video CodingAshfaq Ahmed, Muhammad Usman Shahid, Maurizio Martina, Enrico Magli, Guido Masera. 288-292 [doi]
- A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGAYoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi. 293-296 [doi]
- An Efficient Router Architecture and Its FPGA Prototyping to Support Junction Based Routing in NoC PlatformsMuhammad Awais Aslam, Shashi Kumar, Rickard Holsmark. 297-300 [doi]
- An Efficient FPGA-Based Architecture of Skein for Simple Hashing and MAC FunctionFilippos Pirpilidis, Paris Kitsos, Nicolas Sklavos. 301-304 [doi]
- Implementing Modular FFTs in FPGAs - A Basic Block for Lattice-Based CryptographyTamas Györfi, Octavian Cret, Zalan Borsos. 305-308 [doi]
- An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCsChanglin Chen, Sorin Dan Cotofana. 311-318 [doi]
- Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-ChipEvangelia Kasapaki, Jens Sparsø, Rasmus Bo Sorensen, Kees Goossens. 319-326 [doi]
- Power and Variability Improvement of an Asynchronous Router Using Stacking and Dual-Vth ApproachesMohammad Mirzaei, Mahdi Mosaffa, Siamak Mohammadi, Jelena Trajkovic. 327-334 [doi]
- Emulation-Based Fault Effect Analysis for Resource Constrained, Secure, and Dependable SystemsNorbert Druml, Manuel Menghin, Daniel Kroisleitner, Christian Steger, Reinhold Weiss, Armin Krieg, Holger Bock, Josef Haid. 337-344 [doi]
- Electromagnetic Analysis on RSA Algorithm Based on RNSGuilherme Perin, Laurent Imbert, Lionel Torres, Philippe Maurine. 345-352 [doi]
- Double-Edge Transformation for Optimized Power Analysis Suppression CountermeasuresShohreh Sharif Mansouri, Elena Dubrova. 353-359 [doi]
- parMERASA - Multi-core Execution of Parallelised Hard Real-Time Applications Supporting AnalysabilityTheo Ungerer, Christian Bradatsch, Mike Gerdes, Florian Kluge, Ralf Jahr, Jörg Mische, J. Fernandes, Pavel G. Zaykov, Zlatko Petrov, B. Boddeker, S. Kehr, Hans Regler, A. Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Ian Broster, N. Lay, D. George, Eduardo Quiñones, Milos Panic, Jaume Abella, Francisco J. Cazorla, Sascha Uhrig, M. Rohde, A. Pyka. 363-370 [doi]
- EU FP7-288307 Pharaon Project: Parallel and Heterogeneous Architecture for Real-Time ApplicationsHector Posadas, Eugenio Villar, Florian Broekaert, Michel Bourdellès, Albert Cohen, Antoniu Pop, Nhat Minh Lê, Adrien Guatto, Mihai T. Lazarescu, Luciano Lavagno, Andrei Terechko, Miguel Glassee, Daniel Calvo, Edouardo de las Heras. 371-378 [doi]
- Coarse-Grain Optimization and Code Generation for Embedded Multicore SystemsGeorge Goulas, Christos Valouxis, Panayiotis Alefragis, Nikolaos S. Voros, Christos Gogos, Oliver Oey, Timo Stripf, Thomas Bruckschlögl, Jürgen Becker, Ali El Moussawi, Maxime Naullet, Tomofumi Yuki. 379-386 [doi]
- Distributed Runtime Computation of Constraints for Multiple Inner LoopsNasim Farahini, Ahmed Hemani, Kolin Paul. 389-395 [doi]
- A Formal Model for Optimal Autonomous Task Hibernation in Constrained Embedded SystemsCarlo Brandolese, William Fornaciari, Luigi Rucco. 396-403 [doi]
- Multiobjective Optimization of Cost, Performance and Thermal Reliability in 3DICsFatemeh Kashfi, Jeff Draper. 404-411 [doi]
- Scalable Video Coding Deblocking Filter FPGA and ASIC Implementation Using High-Level Synthesis MethodologyPedro P. Carballo, Omar Espino, Romen Neris, Pedro Hernandez-Fernandez, Tomasz Szydzik, Antonio Núñez. 415-422 [doi]
- Architecture Design and Efficiency Evaluation for the High-Throughput Interpolation in the HEVC EncoderG. Pastuszak, M. Trochimiuk. 423-428 [doi]
- A Novel Intra Prediction Architecture for the Hardware HEVC EncoderAndrzej Abramowski, Grzegorz Pastuszak. 429-436 [doi]
- Minimal Stimuli Generation in Simulation-Based VerificationShuo Yang, Robert Wille, Daniel Große, Rolf Drechsler. 439-444 [doi]
- Simulation and SAT Based ATPG for Compressed Test GenerationJiri Balcarek, Petr Fiser, Jan Schmidt. 445-452 [doi]
- Industrial Application of IEEE P1687 for an Automotive ProductMartin Keim, Tom Waayers, Richard Morren, Friedrich Hapke, Rene Krenz-Baath. 453-461 [doi]
- Execution Time and Code Size Optimization Using Multidimensional Retiming and Loop StripingYaroub Elloumi, Mohamed Akil, Mohamed Bedoui Hedi. 462-466 [doi]
- UML/MARTE Methodology for Automatic SystemC Code Generation of Openmax Multimedia ApplicationsPablo Peñil, Pablo Sanchez, David de la Fuente, Jesús Barba, Juan Carlos López. 467-470 [doi]
- An Efficient Method for Energy Estimation of Application Specific Instruction-Set ProcessorsRoel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal. 471-474 [doi]
- Delay Fault Coverage Increasing in Digital CircuitsMiroslav Siebert, Elena Gramatová. 475-478 [doi]
- Account for Radiation Effects in Signal Integrity Analysis of PCB Digital SystemsK. O. Petrosyants, I. A. Kharitonov. 479-482 [doi]
- Voltage Spikes on the Substrate to Obtain Timing FaultsKarim Tobich, Philippe Maurine, Pierre-Yvan Liardet, Mathieu Lisart, Thomas Ordas. 483-486 [doi]
- An Energy-Efficient Reconfigurable NoC Architecture with RF-InterconnectsMajed ValadBeigi, Farshad Safaei, Bahareh Pourshirazi. 489-496 [doi]
- Monitoring-Aware Virtual Platform Prototype of Heterogeneous NoC-Based Multicore SoCsMiltos D. Grammatikakis, Antonis Papagrigoriou, Polydoros Petrakis, George Kornaros. 497-504 [doi]
- An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on ChipGiuseppe Ascia, Maurizio Palesi, Vincenzo Catania. 505-512 [doi]
- Incorporating Energy and Throughput Awareness in Design Space Exploration and Run-Time Mapping for Heterogeneous MPSoCsPham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung. 513-521 [doi]
- Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability NeedsSyed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen. 525-534 [doi]
- FPGA Based Real-Time Data Processing DAQ System for the Mercury Imaging X-Ray SpectrometerFlorian Aschauer, Walter Stechele, Johannes Treis. 535-542 [doi]
- Component-Level Datapath Merging in System-Level Design of Wireless Sensor Node Controllers for FPGA-Based ImplementationsMuhammad Adeel Pasha, Steven Derrien, Olivier Sentieys. 543-550 [doi]
- Automatic Hard Block Inference on FPGAsAdrian Willenbücher, Klaus Schneider. 551-557 [doi]
- Predictive Analysis of Mission Critical Systems DependabilityMartin Danhel, Hana Kubatova, Radek Dobias. 561-566 [doi]
- A Distributed BIST Scheme for NoC-Based Memory CoresBibhas Ghoshal, Indranil Sengupta. 567-574 [doi]
- The Essence of Reliability Estimation during Operational Life for Achieving High System DependabilityMuhammad Aamir Khan, Hans G. Kerkhoff. 575-581 [doi]
- Cone of Influence Analysis at the Electronic System Level Using Machine LearningJannis Stoppe, Robert Wille, Rolf Drechsler. 582-587 [doi]
- A Multithreaded Parallel Global Routing Method with Overlapped Routing RegionsYasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi. 591-597 [doi]
- Advanced Switching Mechanisms for Forthcoming On-Chip NetworksEmilio Castillo, Cristobal Camarero, Esteban Stafford, Fernando Vallejo, José Luis Bosque, Ramón Beivide. 598-605 [doi]
- Laser-Induced Fault SimulationFeng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 609-614 [doi]
- FPGA Design of an Open-Loop True Random Number GeneratorFlorent Lozach, Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger. 615-622 [doi]
- An Ambient Temperature Variation Tolerance Scheme for an Ultra Low Power Shared-L1 Processor ClusterDaniele Bortolotti, Andrea Bartolini, Luca Benini. 625-632 [doi]
- A Resource Manager for Dynamically Reconfigurable FPGA-Based Embedded SystemsTeresa Cervero, Julio Dondo, A. Gomez, X. Pena, S. Lopez, Fernando Rincón Calle, R. Sarmiento, J. C. López. 633-640 [doi]
- Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge LogicPartha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay. 641-644 [doi]
- Differential Power Analysis under Constrained Budget: Low Cost Education of HackersFilip tepanek, Jiri Bucek, Martin Novotný. 645-648 [doi]
- Compact FPGA-Based Hardware Architectures for GF(2^m) MultipliersMiguel Morales-Sandoval, Arturo Diaz-Perez. 649-652 [doi]
- MISRs for Fast Authentication of Long MessagesRajendra S. Katti, Rucha Sule. 653-657 [doi]
- A Novel Authenticated Encryption Algorithm for RFID SystemsZahra Jeddi, Esmaeil Amini, Magdy Bayoumi. 658-661 [doi]
- Hardware Trojan Protection for Third Party IPsAmr Al-Anwar, Yousra Alkabani, M. Watheq El-Kharashi, Hassan Bedour. 662-665 [doi]
- Development Flow for FPGA-Based Scalable Reconfigurable SystemsJulian Caba, Julio Dondo, Fernando Rincón, Jesús Barba, Juan C. Lopez. 666-669 [doi]
- Wireless Multi-channel Quasi-digital Tactile Sensing Glove-Based SystemPaolo Motto Ros, Marco Crepaldi, Alberto Bonanno, Danilo Demarchi. 673-680 [doi]
- Low Complexity Background Subtraction for Wireless Vision Sensor NodeMuhammad Imran Shahzad, Naeem Ahmad, Khursheed Khursheed, Mattias O'Nils, Najeem Lawal. 681-688 [doi]
- A Low Power 15-Bit Decimator in 0.18um CMOS for Biomedical ApplicationsKristin Scholfield, Tom Chen. 689-694 [doi]
- FPGA PUF Based on Programmable LUT DelaysBilal Habib, Kris Gaj, Jens-Peter Kaps. 697-704 [doi]
- A Security-Enhanced UHF RFID Tag ChipJohann Ertl, Thomas Plos, Martin Feldhofer, Norbert Felber, Luca Henzen. 705-712 [doi]
- A Faster Shift Register Alternative to Filter GeneratorsMing Liu, Shohreh Sharif Mansouri, Elena Dubrova. 713-718 [doi]
- A Scalable Hardware Implementation of a Best-Effort Scheduler for Multicore ProcessorsDaniel Gregorek, Christof Osewold, Alberto García Ortiz. 721-727 [doi]
- A Low-Area Reference-Free Power Supply SensorCarlos Benito, Pablo Ituero, Marisa López-Vallejo. 728-733 [doi]
- Scenario Patterns and Trace-Based Temporal Verification of Reactive Embedded SystemsAlice M. Tokarnia, Emerson P. Cruz. 734-741 [doi]
- Adaptive Equalizer Training for High-Speed Low-Power Communication SystemsYuan Fang, Ling Chen, Ashok Jaiswal, Klaus Hofmann, Peter Gregorius. 745-751 [doi]
- Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication SystemsAshok Jaiswal, Yuan Fang, Peter Gregorius, Klaus Hofmann. 752-758 [doi]
- AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual ConnectionsAurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf. 761-768 [doi]
- Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-ChipRan Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny. 769-776 [doi]
- Morphone.OS: Context-Awareness in Everyday LifeA. A. Nacci, M. Mazzucchelli, Martina Maggio, Alessandra Bonetto, Donatella Sciuto, Marco D. Santambrogio. 779-786 [doi]
- UML-Based Modeling and Simulation of Environmental Effects in Networked Embedded SystemsEmad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia. 787-794 [doi]
- Memristor-Based (ReRAM) Data Memory Architecture in ASIP DesignMatthias Hartmann, Praveen Raghavan, Liesbet Van der Perre, Prashant Agrawal, Wim Dehaene. 795-798 [doi]
- Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage NetworksAngela Souto Vieites, Roberto R. Osorio. 799-802 [doi]
- Capacitive Sensors Matrix for Interface Pressure Measurement in Clinical, Ergonomic and Automotive EnvironmentsElisa Marenzi, Gian Mario Bertolotti, Francesco Leporati, Giovanni Danese. 803-806 [doi]
- Lab on Chip: Portable Optical Device for On-site Multi-parametric AnalysisS. Rampazzi, Giovanni Danese, L. Fornasari, Francesco Leporati, F. Marabelli, Nelson Nazzicari, Armand Valsesia. 807-810 [doi]
- Dataflow-Based Multi-ASIP Platform Approach for Digital Control ApplicationsRaymond Frijns, A. L. J. Kamp, Sander Stuijk, Jeroen Voeten, M. Bontekoe, K. J. A. Gemei, Henk Corporaal. 811-814 [doi]
- pyHybrid Analysis: A Package for Semantics Analysis of Hybrid SystemsAlberto Casagrande, Tommaso Dreossi. 815-818 [doi]
- Instruction Selection and Scheduling for DSP Kernels on Custom ArchitecturesMehmet Ali Arslan, Krzysztof Kuchcinski. 821-828 [doi]
- Register Transfer Level Workflow for Application and Evaluation of Soft Error Mitigation TechniquesFilipe Sousa, Francis Anghinolfi, João Canas Ferreira. 829-835 [doi]
- RAPIDITAS: RAPId Design-Space-Exploration Incorporating Trace-Based Analysis and SimulationAmit Kumar Singh, Anup Das, Akash Kumar. 836-843 [doi]
- Automatic Controller Detection for Large Scale RTL DesignsWei Song 0002, Jim D. Garside. 844-851 [doi]
- Error Correction of Transient Errors in a Sum-Bit Duplicated Adder by Error DetectionStefan Weidling, Egor S. Sogomonyan, Michael Gössel. 855-862 [doi]
- Self-Checking Carry Select Adder with Fault LocalizationMuhammad Ali Akbar, Jeong-A. Lee. 863-869 [doi]
- Area-Time Efficient Self-Checking ALU Based on Scalable Error Detection CodingZahid Ali Siddiqui, Park Hui-Jong, Jeong-A. Lee. 870-877 [doi]
- Effective Online Power Management with Adaptive Interplay of DVS and DPM for Embedded Real-Time SystemGang Chen, Kai Huang, Jia Huang, Christian Buckl, Alois Knoll. 881-889 [doi]
- Energy Consumption Modeling of H.264/AVC Video Decoding for GPP and DSPYahia Benmoussa, Jalil Boukhobza, Eric Senn, Djamel Benazzouz. 890-897 [doi]
- Power and Thermal Fault Effect Exploration Framework for Reader/Smart Card DesignsNorbert Druml, Manuel Menghin, Tobias Rauter, Christian Steger, Reinhold Weiss, Christian Bachmann, Holger Bock, Josef Haid. 898-906 [doi]
- PtNBridge - A Power-Aware and Trustworthy Near Field Communication Bridge to Embedded SystemsManuel Menghin, Norbert Druml, Manuel Trebo Fioriello, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid. 907-914 [doi]
- Master-Slave Control Structure for Massively Parallel System on ChipHana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser. 917-924 [doi]
- Improving Performance and Fabrication Metrics of Three-Dimensional ICs by Multiplexing Through-Silicon ViasMostafa Said, Farhad Mehdipour, Mohamed El-Sayed. 925-932 [doi]
- LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell LibrariesMatheus Trevisan Moreira, Carlos Henrique Menezes Oliveira, Ney Laert Vilar Calazans, Luciano Copello Ost. 933-940 [doi]
- Runtime Online Links Voltage Scaling for Low Energy Networks on ChipAndrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania. 941-944 [doi]
- Glitch Detection in Hardware Implementations on FPGAs Using Delay Based Sampling TechniquesRajesh Velegalati, Kinjal Shah, Jens-Peter Kaps. 947-954 [doi]
- Evaluating the Hardware Performance of a Million-Bit MultiplierYarkin Doroz, Erdinç Öztürk, Berk Sunar. 955-962 [doi]
- PERMS: A Bit Permutation Instruction for Accelerating Software CryptographySouvik Kolay, Sagar Khurana, Anupam Sadhukhan, Chester Rebeiro, Debdeep Mukhopadhyay. 963-968 [doi]
- A Scalable Multiplier for Arbitrary Large Numbers Supporting Homomorphic EncryptionGhada Y. Abozaid, Ahmed El-Mahdy, Yasutaka Wada. 969-975 [doi]
- Fast Multiprocessor Scheduling with Fixed Task Binding of Large Scale Industrial Cyber Physical SystemsShreya Adyanthaya, Marc Geilen, Twan Basten, Ramon R. H. Schiffelers, Bart D. Theelen, Jeroen Voeten. 979-988 [doi]
- Towards a Modelling and Design Framework for Mixed-Criticality SoCs and Systems-of-SystemsFernando Herrera, Seyed Hosein Attarzadeh Niaki, Ingo Sander. 989-996 [doi]
- Passivity-Based Control over Differentiated-Services Packet NetworksGiovanni Lorenzi, Davide Quaglia, Riccardo Muradore, Paolo Fiorini. 997-1004 [doi]
- A Physical-Aware Abstraction Flow for Efficient Design-Space Exploration of a Wireless Body Area Network ApplicationMarco Crepaldi, Paolo Motto Ros, Danilo Demarchi, John Buckley, Brendan O'Flynn, D. Quaglia. 1005-1012 [doi]