Abstract is missing.
- Digital Transformation of Automobile and Mobility ServiceHiroshi Miyata. 1-5 [doi]
- Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision HardwareKota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura. 6-13 [doi]
- A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGAHongxiang Fan, Shuanglong Liu, Martin Ferianc, Ho-Cheung Ng, Zhiqiang Que, Shen Liu, Xinyu Niu, Wayne Luk. 14-21 [doi]
- FPGA Accelerated HPC and Data AnalyticsMike Strickland. 21 [doi]
- Accelerator-in-Switch: A Novel Cooperation Framework for FPGAs and GPUsHideharu Amano. 22 [doi]
- Implementing NEF Neural Networks on Embedded FPGAsBenjamin Morcos, Terrence C. Stewart, Chris Eliasmith, Nachiket Kapre. 22-29 [doi]
- Novel Neural Network Applications on New Python Enabled PlatformsKees A. Vissers. 23 [doi]
- Memory-Efficient Architecture for Accelerating Generative Networks on FPGAShuanglong Liu, Chenglong Zeng, Hongxiang Fan, Ho-Cheung Ng, Jiuxi Meng, Zhiqiang Que, Xinyu Niu, Wayne Luk. 30-37 [doi]
- Live Migration for OpenCL FPGA AcceleratorsAnuj Vaishnav, Khoa Dang Pham, Dirk Koch. 38-45 [doi]
- An Empirically Guided Optimization Framework for FPGA OpenCLAhmed Sanaullah, Rushi Patel, Martin C. Herbordt. 46-53 [doi]
- Software-Specified FPGA Accelerators for Elementary FunctionsJing Chen, Xue Liu, Jason Anderson. 54-61 [doi]
- Scaling Up Loop Pipelining for High-Level Synthesis: A Non-iterative ApproachLeandro de Souza Rosa, Vanderlei Bonato, Christos-Savvas Bouganis. 62-69 [doi]
- Application Acceleration on FPGAs with OmpSs@FPGAJaume Bosch, Xubin Tan, Antonio Filgueras, Miquel Vidal, Marc Mateu, Daniel Jiménez-González, Carlos Álvarez 0001, Xavier Martorell, Eduard Ayguadé, Jesús Labarta. 70-77 [doi]
- FLiMS: Fast Lightweight Merge SorterPhilippos Papaphilippou, Chris Brooks, Wayne Luk. 78-85 [doi]
- Very Massive Hardware Merge SorterMakoto Saitoh, Kenji Kise. 86-93 [doi]
- Stream-Based ORB Feature Extractor with Dynamic Power OptimizationPhong Tran, Thinh Hung Pham, Siew Kei Lam, Meiqing Wu, Bhavan A. Jasani. 94-101 [doi]
- R3SGM: Real-Time Raster-Respecting Semi-Global Matching for Power-Constrained SystemsOscar Rahnama, Tommaso Cavallari, Stuart Golodetz, Simon Walker, Philip H. S. Torr. 102-109 [doi]
- Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved OptimizationKevin E. Murray, Vaughn Betz. 110-117 [doi]
- SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAsChirag Ravishankar, Henri Fraisse, Dinesh Gaitonde. 118-125 [doi]
- Compact Area and Performance Modelling for CGRA Architecture EvaluationKuang Ping Niu, Jason H. Anderson. 126-133 [doi]
- MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel MemoriesKoya Mitsuzuka, Yuta Tokusashi, Hiroki Matsutani. 134-141 [doi]
- Ultra-Low-Latency and Flexible In-memory Key-Value Store System Design on CPU-FPGAYunhui Qiu, Hankun Lv, Jinyu Xie, Wenbo Yin, Lingli Wang. 142-149 [doi]
- A Nearest Neighbor Search Engine Using Distance-Based HashingToshitaka Ito, Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi. 150-157 [doi]
- DaCO: A High-Performance Token Dataflow Coprocessor Overlay for FPGAsSiddhartha 0001, Nachiket Kapre. 158-165 [doi]
- Scheduling Algorithms for High Performance Network Switching on FPGAs: A SurveyNadeen Gebara, Jiuxi Meng, Wayne Luk, Paolo Costa. 166-173 [doi]
- Enabling Overclocking Through Algorithm-Level Error DetectionThibaut Marty, Tomofumi Yuki, Steven Derrien. 174-181 [doi]
- Secure Hardware Kernels Execution in CPU+FPGA Heterogeneous CloudFestus Hategekimana, Joel Mandebi Mbongue, Md Jubaer Hossain Pantho, Christophe Bobda. 182-189 [doi]
- A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVESFarnoud Farahmand, Malik Umar Sharif, Kevin Briggs, Kris Gaj. 190-197 [doi]
- Injecting FPGA Configuration Faults in ParallelShane T. Fleming, David Thomas. 198-205 [doi]
- Evaluating The Highly-Pipelined Intel Stratix 10 FPGA Architecture Using Open-Source BenchmarksTian Tan 0007, Eriko Nurvitadhi, David Shih, Derek Chiou. 206-213 [doi]
- FPGA Architecture Enhancements for Efficient BNN ImplementationJin-Hee Kim, Jongeun Lee, Jason Anderson. 214-221 [doi]
- Synthesizable Heterogeneous FPGA FabricsBrett Grady, Jason Helge Anderson. 222-229 [doi]
- QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System PartitioningSiva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar 0001. 230-233 [doi]
- High-Speed Computation of CRC Codes for FPGAsJakub Cabal, Lukás Kekely, Jan Korenek. 234-237 [doi]
- FCLNN: A Flexible Framework for Fast CNN Prototyping on FPGA with OpenCL and CaffeXianchao Xu, Brian Liu. 238-241 [doi]
- Accelerating Top-k ListNet Training for Ranking Using FPGAQiang Li, Shane T. Fleming, David Thomas, Peter Cheung. 242-245 [doi]
- GridGAS: An I/O-Efficient Heterogeneous FPGA+CPU Computing Platform for Very Large-Scale Graph AnalyticsYu Zou, Mingjie Lin. 246-249 [doi]
- Lossy Multiport MemoryBowen P. Y. Kwan, Gary C. T. Chow, Tim Todman, Wayne Luk, Wenguang Xu. 250-253 [doi]
- An FPGA Implementation of Robust MattingTakuya Yamazaki, Tsutomu Maruyama. 254-257 [doi]
- Improving Confidentiality in Virtualized FPGAsSadegh Yazdanshenas, Vaughn Betz. 258-261 [doi]
- High Performance High-Precision Floating-Point Operations on FPGAs Using OpenCLNaohito Nakasato, Hiroshi Daisaka, Tadashi Ishikawa. 262-265 [doi]
- Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAsTobias Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck. 266-269 [doi]
- FPGA Acceleration of a Supervised Learning Method for Hyperspectral Image ClassificationKento Tajiri, Tsutomu Maruyama. 270-273 [doi]
- High Throughput CNN Accelerator Design Based on FPGALiang Xie, Xitian Fan, Wei Cao, Lingli Wang. 274-277 [doi]
- Hardware-Accelerated Index Construction for Semantic WebChristopher Blochwitz, Julian Wolff, Mladen Berekovic, Dennis Heinrich, Sven Groppe, Jan Moritz Joseph, Thilo Pionteck. 278-281 [doi]
- DP-Pack: Distributed Parallel Packing for FPGAsQiangpu Chen, Minghua Shen, Nong Xiao. 282-285 [doi]
- Checking for Electrical Level Security Threats in Bitstreams for Multi-tenant FPGAsDennis R. E. Gnad, Sascha Rapp, Jonas Krautter, Mehdi Baradaran Tahoori. 286-289 [doi]
- An Accelerated OpenVX Overlay for Pure Software ProgrammersHossein Omidian, Nick Ivanov, Guy G. F. Lemieux. 290-293 [doi]
- Mapping Estimator for OpenCL Heterogeneous AcceleratorsAndré Bannwart Perina, Vanderlei Bonato. 294-297 [doi]
- A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object DetectorHiroki Nakahara, Masayuki Shimoda, Shimpei Sato. 298-301 [doi]
- Investigating How Hardware Architectures are Expressed in High-Level Languages for an SKA AlgorithmKrystine Dawn Sherwin, Ben Stappers, Prabu Thiagaraj, Kevin I-Kai Wang, Oliver Sinnen. 302-305 [doi]
- Simultaneous Inference and Training Using On-FPGA Weight Perturbation TechniquesSiddhartha 0003, Steven J. E. Wilton, David Boland, Barry Flower, Perry Blackmore, Philip H. W. Leong. 306-309 [doi]
- An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural NetworkAkira Jinguji, Tomoya Fujii, Shimpei Sato, Hiroki Nakahara. 310-313 [doi]
- Performance Estimation for Exascale Reconfigurable Dataflow PlatformsRyota Yasudo, José Gabriel F. Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker. 314-317 [doi]
- Lattice-Based Scheduling for Multi-FPGA SystemsTeng Yu, Bo Feng, Mark Stillwell, Liucheng Guo, Yuchun Ma, John Thomson. 318-321 [doi]
- ReFiRe: Efficient Deployment of Remote Fine-Grained Reconfigurable AcceleratorsEmmanouil Pissadakis, Nikolaos Alachiotis, Panagiotis Skrimponis, Dimitris Theodoropoulos, Thanasis Korakis, Dionisios N. Pnevmatikatos. 322-325 [doi]
- AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAsJorge Echavarria, Stefan Wildermann, Jürgen Teich. 326-329 [doi]
- Face-off Between the CAESAR Lightweight Finalists: ACORN vs. AsconFarnoud Farahmand, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj. 330-333 [doi]
- Large Utility Sorting on FPGAsKristiyan Manev, Dirk Koch. 334-337 [doi]
- A System-Level Transprecision FPGA Accelerator for BLSTM Using On-chip Memory ReshapingDionysios Diamantopoulos, Christoph Hagleitner. 338-341 [doi]
- Transparent Acceleration of Image Processing Kernels on FPGA-Attached Hybrid Memory Cube ComputersMd Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews. 342-345 [doi]
- A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA PlatformWenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao. 346-349 [doi]
- Distributed-Memory Based FPGA Debug: Design Timing ImpactRobert Hale, Brad L. Hutchings. 350-353 [doi]
- Unified On-Chip Software and Hardware Debug for HLS-Accelerated ProgramsMatthew B. Ashcraft, Jeffrey Goeders. 354-357 [doi]
- Optimisation of Convolution of Multiple Different Sized Filters in SKA Pulsar Search EngineHaomiao Wang, Ben Stappers, Prabu Thiagaraj, Oliver Sinnen. 358-361 [doi]
- Speed and Resource Optimization of BFGS Quasi-Newton Implementation on FPGA Using Inexact Line Search Method for Neural Network TrainingJia Liu, Qiang Liu. 362-365 [doi]
- A Short-Transfer Model for Tightly-Coupled CPU-FPGA PlatformsAlexander Kroh, Oliver Diessel. 366-369 [doi]
- An Automated FPGA-Based Fault Injection Platform for Granularly-Pipelined Fault Tolerant CORDICYu Xie, He Chen, Yizhuang Xie, Chuang-An Mao, Bingyi Li. 370-373 [doi]
- An Area-Efficient Out-of-Order Soft-Core Processor Without Register RenamingJunichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai. 374-377 [doi]
- Enhancing Memory Bandwidth in a Single Stream Computation with Multiple FPGAsAntoniette Mondigo, Kentaro Sano, Hiroyuki Takizawa. 378-380 [doi]
- Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps ThroughputLukás Kekely, Martin Spinler, Stepán Friedl, Jiri Sikora, Jan Korenek, Viktor Pus. 381-384 [doi]
- Lens Distortion Self-Calibration Using the Hough TransformDonald Bailey, Yuan Chang, Steven Le Moan. 385-388 [doi]
- Real-Time Object Detection and Semantic Segmentation Hardware System with Deep Learning NetworksShaoxia Fang, Lu Tian, Junbin Wang, Shuang Liang, Dongliang Xie, Zhongmin Chen, Lingzhi Sui, Qian Yu, Xiaoming Sun, Yi Shan, Yu Wang. 389-392 [doi]
- LeFlow: Automatic Compilation of TensorFlow Machine Learning Applications to FPGAsDaniel Holanda Noronha, Kahlan Gibson, Bahar Salehpour, Steven J. E. Wilton. 393-396 [doi]
- Introduction of MNSTbotKyosuke Mori, Yuuki Saitoh, Naohito Nakasato. 397-399 [doi]
- Development of an FPGA Controlled "Mini-Car" Toward Autonomous DrivingMusashi Aoto, Yasutaka Wada, Yousuke Numata. 400-402 [doi]
- A Platform on All-Programmable SoC for Micro Autonomous RobotsYuya Kudo, Atsushi Takada, Soji Tsuda, Takumi Sakai, Tomonori Izumi. 403-406 [doi]
- Implementation of an Autonomous Driving System for FPT2018 FPGA Design Competition Using the Zynqberry Processing BoardYohei Shimmyo, Maiko Arakawa, Shunsuke Mie, Hiroaki Saito, Yuichi Okuyama, Hiroki Yomogita. 407-410 [doi]
- Development of an Autonomous Driving Robot Car Using FPGAAkira Kojima, Yohei Nose. 411-414 [doi]
- Development of a Robot Car by Single Line Search Method for White Line Detection with FPGAHiromichi Wakatsuki, Takao Kido, Kenta Arai, Yuhei Sugata, Kanemitsu Ootsu, Takashi Yokota, Takeshi Ohkawa. 415-418 [doi]
- Development of a Control Target Recognition for Autonomous Vehicle Using FPGA with PythonHiroki Bingo. 419-420 [doi]
- A Study on Introducing FPGA to ROS Based Autonomous Driving SystemYasuhiro Nitta, Sou Tamura, Hideki Takase. 421-424 [doi]
- FPGA Design for Autonomous Vehicle Driving Using Binarized Neural NetworksKaijie Wei, Koki Honda, Hideharu Amano. 425-428 [doi]