Abstract is missing.
- FPGA design productivity a discussion of the state of the art and a research agendaBrent Nelson. [doi]
- Re-visiting the challenges of programmable concurrent architecturesPatrick Lysaght. [doi]
- FPGA timing, power, signal integrity and other challenges at 65 and 45 nmPaul Leventis. [doi]
- Co-optimisation of datapath and memory in outer loop pipeliningKieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos. 1-8 [doi]
- Wave-pipelined signaling for on-FPGA communicationTerrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk. 9-16 [doi]
- Portable and scalable FPGA-based acceleration of a direct linear system solverWei Zhang, Vaughn Betz, Jonathan Rose. 17-24 [doi]
- A system-level stochastic circuit generator for FPGA architecture evaluationCindy Mark, Ava Shui, Steven J. E. Wilton. 25-32 [doi]
- An FPGA-specific approach to floating-point accumulation and sum-of-productsFlorent de Dinechin, Bogdan Pasca, Octavian Cret, Radu Tudoran. 33-40 [doi]
- Optimizing residue arithmetic on FPGAsHaohuan Fu, Oskar Mencer, Wayne Luk. 41-48 [doi]
- Reconfigurable array for transcendental functions calculationMihai Sima, Michael McGuire, Scott Miller. 49-56 [doi]
- Optimizing coarse-grained units in floating point hybrid FPGAChi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton. 57-64 [doi]
- Hardware acceleration of approximate palindromes searchingTomás Martínek, Matej Lexa. 65-72 [doi]
- PERG: A scalable FPGA-based pattern-matching engine with consolidated Bloomier filtersJohnny Tsung Lin Ho, Guy G. F. Lemieux. 73-80 [doi]
- Design and implementation of a high performance financial Monte-Carlo simulation engine on an FPGA supercomputerXiang Tian, Khaled Benkrid. 81-88 [doi]
- Estimation of sample mean and variance for Monte-Carlo simulationsDavid B. Thomas, Wayne Luk. 89-96 [doi]
- Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domainOliver Sander, Michael Hübner, Jürgen Becker, Matthias Traub. 97-104 [doi]
- A transition probability based delay measurement method for arbitrary circuits on FPGAsJustin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung. 105-112 [doi]
- A profiler for a heterogeneous multi-core multi-FPGA systemDaniel Nunes, Manuel Saldaña, Paul Chow. 113-120 [doi]
- Defining neighborhood relations for fast spatial-temporal partitioning of applications on reconfigurable architecturesJoon Edward Sim, Tulika Mitra, Weng-Fai Wong. 121-128 [doi]
- Accelerating hardware simulation: Testbench code emulationIakovos Mavroidis, Ioannis Papaefstathiou. 129-136 [doi]
- Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processorsTakuro Nakamura, Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano. 137-144 [doi]
- A scalable reconfiguration mechanism for fast dynamic reconfigurationHeiko Hinkelmann, Peter Zipf, Manfred Glesner. 145-152 [doi]
- Memory security management for reconfigurable embedded systemsRomain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Deepak Unnikrishnan, Kris Gaj. 153-160 [doi]
- ACS: An Addressless Configuration Support for efficient partial reconfigurationsJenny Yi-Chun Kuo, Anderson Kuei-An Ku, Jingling Xue, Oliver Diessel, Usama Malik. 161-168 [doi]
- An adaptive pattern recognition hardware with on-chip shift register-based partial reconfigurationHiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga, Kyrre Glette, Jim Tørresen. 169-176 [doi]
- A run-length based connected component algorithm for FPGA implementationKofi Appiah, Andrew Hunter, Patrick Dickinson, Jonathan Owens. 177-184 [doi]
- Optimised single pass connected components analysisNi Ma, Donald G. Bailey, Christopher T. Johnston. 185-192 [doi]
- Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAsHirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. 193-200 [doi]
- FPGA implementation and analysis of random delay insertion countermeasure against DPAYingxi Lu, Máire O'Neill, John V. McCanny. 201-208 [doi]
- Netlist-level IP protection by watermarking for LUT-based FPGAsMoritz Schmid, Daniel Ziener, Jürgen Teich. 209-216 [doi]
- Modelling and compensating for clock skew variability in FPGAsN. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung. 217-224 [doi]
- Kernel sharing on reconfigurable multiprocessor systemsPhilip Garcia, Katherine Compton. 225-232 [doi]
- Evaluating the impact of customized instruction set on coarse grained reconfigurable arraysJulio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel. 233-240 [doi]
- Balanced allocation of compute time in hardware-accelerated systemsWenyin Fu, Katherine Compton. 241-248 [doi]
- Processor customization for wearable bio-monitoring platformsHuynh Phung Huynh, Tulika Mitra. 249-252 [doi]
- An implementation of a watershed algorithm based on connected components on FPGADang Ba Khac Trieu, Tsutomu Maruyama. 253-256 [doi]
- A new flexible PR domain model to replace the fixed multi-PR region model for DPR systemsEdward Chen, Dorian Sabaz, William A. Gruver, Lesley Shannon. 257-260 [doi]
- Exploring hard and soft networks-on-chip for FPGAsRosemary M. Francis, Simon W. Moore. 261-264 [doi]
- An approach for downscaling images for real-time pattern detectionYoshifumi Tanida, Tsutomu Maruyama. 265-268 [doi]
- Dynamically programmable Reed Solomon processor with embedded Galois Field multiplierAhmed O. El-Rayis, Xin Zhao, Tughrul Arslan, Ahmet T. Erdogan. 269-272 [doi]
- Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computationKazuya Tanigawa, Tetsuo Hironaka. 273-276 [doi]
- Synthesis of efficiently reconfigurable datapaths for reconfigurable computingMarkus Rullmann, Renate Merker. 277-280 [doi]
- Makespan minimization in automatic synthesis of multiprocessor systems from parallel programsHarold Ishebabi, Philipp Mahr, Christophe Bobda. 281-284 [doi]
- A new coarse-grained FPGA architecture exploration environmentHusain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez. 285-288 [doi]
- An analog reconfiguration-period adjustment technique for optically reconfigurable gate arraysTakayuki Mabuchi, Minoru Watanabe. 289-292 [doi]
- An 11, 424-gate dynamic optically reconfigurable gate array VLSIMao Nakajima, Minoru Watanabe. 293-296 [doi]
- A systolic regular expression pattern matching engine and its application to network intrusion detectionYosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama. 297-300 [doi]
- Evaluating power and energy consumption of FPGA-based custom computing machines for scientific floating-point computationKentaro Sano, Takeshi Nishikawa, Takayuki Aoki, Satoru Yamamoto. 301-304 [doi]
- A dynamically reconfigurable Field Programmable Gate Array hardware foundation for security applicationsSamuel J. Stone, Roy Porter, Yong C. Kim, Jason V. Paul. 305-308 [doi]
- Quad-level bit-stream signal processing on FPGAsChiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng. 309-312 [doi]
- A low power reconfigurable heterogeneous architecture for a mobile SDR systemZong Wang, Tughrul Arslan. 313-316 [doi]
- High level quantitative interconnect estimation for Early Design Space ExplorationRoel Meeuws, Kamana Sigdel, Yana Yankova, Koen Bertels. 317-320 [doi]
- Unrolling-based loop mapping and schedulingYuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong. 321-324 [doi]
- Concurrent timing based and routability driven depopulation technique for FPGA packingAudip Pandit, Lakshmi Easwaran, Ali Akoglu. 325-328 [doi]
- Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating techniqueYoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano. 329-332 [doi]
- Extending Booth algorithm to multiplications of three numbers on FPGAsYosi Ben-Asher, Esti Stein. 333-336 [doi]
- A scalable FPGA architecture for non-linear SVM trainingMarkos Papadonikolakis, Christos-Savvas Bouganis. 337-340 [doi]
- A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA systemKazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 341-344 [doi]
- Creating digital fingerprints on commercial field programmable gate arraysJames W. Crouch, Hiren J. Patel, Yong C. Kim, J. Todd McDonald, Tony C. Kim. 345-348 [doi]
- An area-efficient FPGA realisation of a codebook-based image compression methodPeter Zipf, Heiko Hinkelmann, Hui Shao, Radu Dogaru, Manfred Glesner. 349-352 [doi]
- A floating-point solver for band structured linear equationsAntonio Roldao Lopes, George A. Constantinides, Eric C. Kerrigan. 353-356 [doi]
- m)Samuel Antao, Ricardo Chaves, Leonel Sousa. 357-360 [doi]
- An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designsWayne Chen, Lesley Shannon. 361-364 [doi]
- Delay evaluation of 90nm CMOS multi-context FPGA with shift-register-type temporal communication module for large-scale circuit emulationNaoto Miyamoto, Tadahiro Ohmi. 365-368 [doi]
- p-VEX: A reconfigurable and extensible softcore VLIW processorStephan Wong, Thijs van As, Geoffrey Brown. 369-372 [doi]
- Automatic generation of decomposition based matrix inversion architecturesAli Irturk, Bridget Benson, Arash Arfaee, Ryan Kastner. 373-376 [doi]
- Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSIShinichi Kato, Minoru Watanabe. 377-380 [doi]
- Real-time FPGA architecture of extended linear convolution for digital image scalingChung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Wen-Kai Tsai, Zeng-chuan Wu. 381-384 [doi]