Henry Block - researchr alias

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Viewing Publication 1 - 5 from 5

2017

An FPGA hardware implementation approach for a phylogenetic tree reconstruction algorithm with incremental tree optimizationHenry Block, Tsutomu Maruyama. fpl 2017: 1-8 [doi]

FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony AlgorithmHenry Block, Tsutomu Maruyama. ieicet, 100-D(2):256-264, 2017. [doi]

2015

An FPGA implementation of a phylogenetic tree reconstruction algorithm using an alternative second-pass optimizationHenry Block, Tsutomu Maruyama. fpl 2015: 1-4 [doi]

2014

An FPGA hardware acceleration of the indirect calculation of tree lengths method for phylogenetic tree reconstructionHenry Block, Tsutomu Maruyama. fpl 2014: 1-4 [doi]

2013

A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGAHenry Block, Tsutomu Maruyama. fpt 2013: 318-321 [doi]

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