Table of Contents

• Leakage and performance aware resource management for 2D dynamically reconfigurable FPGA architecturesSiqi Wang, Pham Nam Khanh, Amit Kumar Singh, Akash Kumar. 1-4 [doi]
• Efficient multi-standard cognitive radios on FPGAsThinh H. Pham, Suhaib A. Fahmy, Ian Vince McLoughlin. 1-2 [doi]
• Caching memcached at reconfigurable network interfaceEric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura. 1-6 [doi]
• Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAsErnesto Sánchez, Luca Sterpone, Anees Ullah. 1-6 [doi]
• Transparent insertion of latency-oblivious logic onto FPGAsEddie Hung, Tim Todman, Wayne Luk. 1-8 [doi]
• Comparing soft and hard vector processing in FPGA-based embedded systemsSoh Jun Jie, Nachiket Kapre. 1-7 [doi]
• A fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning techniqueAli Ebrahim, Tughrul Arslan, Xabier Iturbe. 1-4 [doi]
• The LEAP FPGA operating systemKermin Fleming, Hsin-Jung Yang, Michael Adler, Joel S. Emer. 1-8 [doi]
• Ultrasmall: The smallest MIPS soft processorHiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise. 1-4 [doi]
• Accurate power control and monitoring in ZYNQ boardsArash Farhadi Beldachi, José L. Núñez-Yáñez. 1-4 [doi]
• Compiling text analytics queries to FPGAsRaphael Polig, Kubilay Atasu, Heiner Giefers, Laura Chiticariu. 1-6 [doi]
• Source-level debugging for FPGA high-level synthesisNazanin Calagar, Stephen Dean Brown, Jason Helge Anderson. 1-8 [doi]
• RAM-based hardware accelerator for network data anonymizationFumito Yamaguchi, Kanae Matsui, Hiroaki Nishi. 1-4 [doi]
• Incremental distributed trigger insertion for efficient FPGA debugFatemeh Eslami, Steven J. E. Wilton. 1-4 [doi]
• Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory useJasmina Vasiljevic, Paul Chow. 1-8 [doi]
• Fast and accurate SEU-tolerance characterization method for Zynq SoCsIgor Villata, Unai Bidarte, Uli Kretzschmar, Armando Astarloa, Jesús Lázaro. 1-4 [doi]
• Enabling SRAM-PUFs on Xilinx FPGAsAlexander Wild, Tim Güneysu. 1-4 [doi]
• A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architecturesChristian Fobel, Gary William Grewal, Deborah Stacey. 1-8 [doi]
• High throughput channel tracking for JTRS wireless channel emulationDajung Lee, Janarbek Matai, Brad T. Weals, Ryan Kastner. 1-4 [doi]
• Educating hardware design - From primary school children to postgraduate engineersOliver Knodel, Martin Zabel, Patrick Lehmann, Rainer G. Spallek. 1-4 [doi]
• Low-cost multiplier-based FPU for embedded processing on FPGABogdan Pasca. 1-4 [doi]
• HyPER: A runtime reconfigurable architecture for monte carlo option pricing in the Heston modelChristian Brugger, Christian de Schryver, Norbert Wehn. 1-8 [doi]
• An efficient FPGA-based hardware framework for natural feature extraction and related Computer Vision tasksMatthias Pohl, Michael Schaeferling, Gundolf Kiefer. 1-8 [doi]
• Dataflow acceleration of Krylov subspace sparse banded problemsPavel Burovskiy, Stephen Girdlestone, Craig Davies, Spencer J. Sherwin, Wayne Luk. 1-6 [doi]
• An efficient sparse conjugate gradient solver using a Beneš permutation networkGary C. T. Chow, Paul Grigoras, Pavel Burovskiy, Wayne Luk. 1-7 [doi]
• FPGA implementation of low-power split-radix FFT processorsZhuo Qian, Nasibeh Nasiri, Oren Segal, Martin Margala. 1-2 [doi]
• Power-efficient re-gridding architecture for accelerating Non-uniform Fast Fourier TransformUmer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar. 1-6 [doi]
• Multi-FPGA reconfigurable system for accelerating MATLAB simulationsMuhammed Al Kadi, Max Ferger, Volker Stegemann, Michael Hübner. 1-4 [doi]
• Methods for implementation of feedback loops in high speed FPGA applicationsNima Safari, Volker Mauer, Shahin Gheitanchi. 1-4 [doi]
• A scalable, high-performance customized priority queueMuhuan Huang, Kevin Lim, Jason Cong. 1-4 [doi]
• A soft-core processor for finite field arithmetic with a variable word size acceleratorAiko Iwasaki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa. 1-4 [doi]
• FPGA architecture support for heterogeneous, relocatable partial bitstreamsChristophe Huriaux, Olivier Sentieys, Russell Tessier. 1-6 [doi]
• New approaches for in-system debug of behaviorally-synthesized FPGA circuitsJoshua S. Monson, Brad L. Hutchings. 1-6 [doi]
• High level programming framework for FPGAs in the data centerOren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright. 1-4 [doi]
• Application specific multi-port memory customization in FPGAsGorker Alp Malazgirt, Hasan Erdem Yantir, Arda Yurdakul, Smaïl Niar. 1-4 [doi]
• Secure partial dynamic reconfiguration with unsecured external memoryHirak Kashyap, Ricardo Chaves. 1-7 [doi]
• Accelerate NDN name lookup using FPGA: Challenges and a scalable approachYanbiao Li, Dafang Zhang, Xian Yu, Wei Liang, Jing Long, Hong Qiao. 1-4 [doi]
• Interconnect for commodity FPGA clusters: Standardized or customized?A. Theodore Markettos, Paul J. Fox, Simon W. Moore, Andrew W. Moore. 1-8 [doi]
• FPGA acceleration of SAT/Max-SAT solving using variable-way cacheKenji Kanazawa, Tsutomu Maruyama. 1-4 [doi]
• Experimental multi-FPGA GNSS receiver platformFabio Garzia, Alexander Rügamer, Robert Koch, Philipp Neumaier, Ekaterina Serezhkina, Matthias Overbeck, Günter Rohmer. 1-4 [doi]
• Method for dynamic power monitoring on FPGAsMohamad Najem, Pascal Benoit, Florent Bruguier, Gilles Sassatelli, Lionel Torres. 1-6 [doi]
• Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoringLukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek. 1-4 [doi]
• Aging effects in FPGAs: an experimental analysisAbdulazim Amouri, Florent Bruguier, Saman Kiamehr, Pascal Benoit, Lionel Torres, Mehdi Baradaran Tahoori. 1-4 [doi]
• Achieving portability and efficiency over chip heterogeneous multiprocessor systemsEugene Cartwright, Alborz Sadeghian, Sen Ma, David L. Andrews. 1-4 [doi]
• A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technologyToru Katagiri, Hideharu Amano. 1-4 [doi]
• Mixed-architecture process scheduling on tightly coupled reconfigurable computersBrandon Kyle Hamilton, Michael Inggs, Hayden Kwok-Hay So. 1-4 [doi]
• A high performance alternating projections image demosaicing hardwareHasan Azgin, Serkan Yaliman, Ilker Hamzaoglu. 1-4 [doi]
• Particle filtering-based Maximum Likelihood Estimation for financial parameter estimationJinzhe Yang, Binghuan Lin, Wayne Luk, Terence Nahar. 1-4 [doi]
• TransPar: Transformation based dynamic Parallelism for low power CGRAsSyed M. A. H. Jafri, Guilermo Serrano, Masoud Daneshtalab, Naeem Abbas, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen. 1-8 [doi]
• A semi-supervised modeling approach for performance characterization of FPGA architecturesLiqun Yang, Haigang Yang, Wei Li, Zhihua Li, Zhihong Huang, Colin Yu Lin. 1-6 [doi]
• Rapid codesign of a soft vector processor and its compilerMatthew Naylor, Simon W. Moore. 1-4 [doi]
• Pipelined compressor tree optimization using integer linear programmingMartin Kumm, Peter Zipf. 1-8 [doi]
• Towards domain-specific Instruction-Set GenerationAdithya Pulli, Carlo Galuzzi, Georgi Gaydadjiev. 1-4 [doi]
• Efficient mapping of mathematical expressions into DSP blocksBajaj Ronak, Suhaib A. Fahmy. 1-4 [doi]
• Modulo SDC scheduling with recurrence minimization in high-level synthesisAndrew Canis, Stephen Dean Brown, Jason Helge Anderson. 1-8 [doi]
• A secure and unclonable embedded system using instruction-level PUF authenticationJason Xin Zheng, Dongfang Li, Miodrag Potkonjak. 1-4 [doi]
• Patra: Parallel tree-reweighted message passing architectureWenlai Zhao, Haohuan Fu, Guangwen Yang, Wayne Luk. 1-6 [doi]
• FPGA acceleration of short read mapping based on sort and parallel comparisonYoukou Sogabe, Tsutomu Maruyama. 1-4 [doi]
• PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systemsTuan D. A. Nguyen, Akash Kumar. 1-6 [doi]
• A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAsShyamsundar Venkataraman, Rui Santos, Anup Das 0001, Akash Kumar. 1-4 [doi]
• Run-time accelerator binding for tile-based mixed-grained reconfigurable architecturesCláudio Machado Diniz, Muhammad Shafique, Sergio Bampi, Jörg Henkel. 1-4 [doi]
• Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithmP. Leyva, Ginés Doménech-Asensi, J. Garrigos, J. Illade-Quinteiro, Victor M. Brea, P. López, Diego Cabello. 1-4 [doi]
• Automatic high-level synthesis of multi-threaded hardware acceleratorsJens Huthmann, Julian Oppermann, Andreas Koch 0001. 1-4 [doi]
• Heterogeneous dataflow architectures for FPGA-based sparse LU factorizationSiddhartha, Nachiket Kapre. 1-4 [doi]
• Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfigurationAndreas Becher, Florian Bauer, Daniel Ziener, Jürgen Teich. 1-8 [doi]
• A mixed integer linear programming approach for design space exploration in FPGA-based MPSoCBouthaina Damak, Rachid Benmansour, Smaïl Niar, Mouna Baklouti, Mohamed Abid. 1-4 [doi]
• Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfigurationJames J. Davis, Peter Y. K. Cheung. 1-6 [doi]
• A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAsMarcin Rogawski, Ekawat Homsirikamol, Kris Gaj. 1-8 [doi]
• Towards dark silicon era in FPGAs using complementary hard logic designAli Ahari, Behnam Khaleghi, Zahra Ebrahimi, Hossein Asadi, Mehdi Baradaran Tahoori. 1-6 [doi]
• Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlaysDavor Capalija, Tarek S. Abdelrahman. 1-8 [doi]
• Area implications of memory partitioning for high-level synthesis on FPGAsLuca Gallo, Alessandro Cilardo, David Thomas, Samuel Bayliss, George A. Constantinides. 1-4 [doi]
• flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platformsShinya Takamaeda-Yamazaki, Kenji Kise. 1-4 [doi]
• Hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoCMarcin Pietras. 1-4 [doi]
• An image processing library for C-based high-level synthesisMoritz Schmid, Nicolas Apelt, Frank Hannig, Jürgen Teich. 1-4 [doi]
• Pattern-based FPGA logic block and clustering algorithmXifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 1-4 [doi]
• Hardware system synthesis from Domain-Specific LanguagesNithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne. 1-8 [doi]
• Privacy preserving large scale DNA read-mapping in MapReduce framework using FPGAsLei Xu, Han-Yee Kim, Xi Wang, Weidong Shi, Taeweon Suh. 1-4 [doi]
• Automated framework for FPGA-based parallel genetic algorithmsLiucheng Guo, David B. Thomas, Ce Guo, Wayne Luk. 1-7 [doi]
• An enhanced and embedded GNU radio flowRyan Marlow, Chris Dobson, Peter Athanas. 1-4 [doi]
• Effective FPGA debug for high-level synthesis generated circuitsJeffrey B. Goeders, Steven J. E. Wilton. 1-8 [doi]
• A highly-efficient and green data flow engine for solving euler atmospheric equationsLin Gan, Haohuan Fu, Chao Yang, Wayne Luk, Wei Xue, Oskar Mencer, Xiaomeng Huang, Guangwen Yang. 1-6 [doi]
• A combination of multi-edge coding and independent coding lines for time-to-digital conversionDominik Sondej, Ryszard Szplet. 1-2 [doi]
• Exploring architecture parameters for dual-output LUT based FPGAsZhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang. 1-6 [doi]
• Improving FPGA accelerated tracking with multiple online trained classifiersMatthew Jacobsen, Siddarth Sampangi, Yoav Freund, Ryan Kastner. 1-7 [doi]
• Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement dataFarnaz Gharibian, Lesley Shannon, Peter Jamieson. 1-6 [doi]
• Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancyAdrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri. 1-4 [doi]
• Pipelined reconfigurable multiplication with constants on FPGAsKonrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf. 1-6 [doi]
• Trends of CPU, GPU and FPGA for high-performance computingMário P. Véstias, Horácio C. Neto. 1-6 [doi]
• Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systemsRoland Dobai. 1-6 [doi]
• Multi-directional error correction schemes for SRAM-based FPGAsShyamsundar Venkataraman, Rui Santos, Sidharth Maheshwari, Akash Kumar. 1-8 [doi]
• Using an OpenCL framework to evaluate interconnect implementations on FPGAsVincent Mirian, Paul Chow. 1-4 [doi]
• A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical SystemsJuan Valverde, A. Rodriguez, Julio Camarero, A. Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo. 1-4 [doi]
• An FPGA sliding window-based architecture harris corner detectorAlexandru Amaricai, Constantina-Elena Gavriliu, Oana Boncalo. 1-4 [doi]
• High-level synthesis-based design methodology for Dynamic Power-Gated FPGAsRehan Ahmed, Assem A. M. Bsoul, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas. 1-4 [doi]
• Asynchronously assisted FPGA for variabilityHock Soon Low, Delong Shang, Fei Xia, Alexandre Yakovlev. 1-4 [doi]
• Criticality-aware scrubbing mechanism for SRAM-based FPGAsRui Santos, Shyamsundar Venkataraman, Anup Das 0001, Akash Kumar. 1-8 [doi]
• FPGA implementation of a multi-algorithm parallel FEC for SDR platformsZhenzhi Wu, Dake Liu, Zheng Yang, Qingying Wang, Wei Zhou. 1-6 [doi]
• Ready PCIe data streaming solutions for FPGAsThomas B. Preußer, Rainer G. Spallek. 1-4 [doi]
• Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCsShane T. Fleming, David B. Thomas. 1-6 [doi]
• Biomedical image processing and reconstruction with dataflow computing on FPGAsFrederik Grüll, Udo Kebschull. 1-2 [doi]
• A survey of open source processors for FPGAsRui Jia, Colin Yu Lin, Zhenhong Guo, Rui Chen, Fei Wang, Tongqiang Gao, Haigang Yang. 1-6 [doi]
• An empirical evaluation of High-Level Synthesis languages and tools for database accelerationOriol Arcas-Abella, Geoffrey Ndu, Nehir Sönmez, Mohsen Ghasempour, Adrià Armejach, Javier Navaridas, Wei Song 0002, John Mawer, Adrián Cristal, Mikel Luján. 1-8 [doi]
• An FPGA hardware acceleration of the indirect calculation of tree lengths method for phylogenetic tree reconstructionHenry Block, Tsutomu Maruyama. 1-4 [doi]
• Efficient 3D triangulation in hardware for dense structure-from-motion in low-speed automotive scenariosStefan Wonneberger, Max Kohler, Wojciech Derendarz, Thorsten Graf, Rolf Ernst. 1-6 [doi]
• Radix-4 and radix-8 booth encoded interleaved modular multipliers over general FpKhalid Javeed, Xiaojun Wang. 1-6 [doi]
• Scalable parallel architecture for singular value decomposition of large matricesUnai Martinez-Corral, Koldo Basterretxea, Raul Finker. 1-4 [doi]
• An efficient and flexible host-FPGA PCIe communication libraryJian Gong, Tao Wang, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu, Jason Cong. 1-6 [doi]
• Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processorChen Yang, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, Shaojun Wei. 1-4 [doi]
• High-throughput implementation of a million-point sparse Fourier TransformAbhinav Agarwal, Haitham Hassanieh, Omid Abari, Ezzeldin Hamed, Dina Katabi, Arvind. 1-6 [doi]
• A hardware/software infrastructure for performance monitoring on LEON3 multicore platformsNam Ho, Paul Kaufmann, Marco Platzner. 1-4 [doi]
• Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processingOana Boncalo, Alexandru Amaricai, Andrei Hera, Valentin Savin. 1-6 [doi]
• THOR - The hardware onion routerTim Güneysu, Francesco Regazzoni, Pascal Sasdrich, Marcin Wójcik. 1-4 [doi]
• An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applicationsMichael Kunz, Alexander Ostrowski, Peter Zipf. 1-4 [doi]
• HPC-gSpan: An FPGA-based parallel system for frequent subgraph miningAthanasios Stratikopoulos, Grigorios Chrysos, Ioannis Papaefstathiou, Apostolos Dollas. 1-4 [doi]
• Using high-level knowledge to enhance data channels in FPGA streaming systemsMarlon Wijeyasinghe, David Thomas. 1-2 [doi]
• Hardware accelerated novel optical de novo assembly for large-scale genomesPingfan Meng, Matthew Jacobsen, Motoki Kimura, Vladimir Dergachev, Thomas Anantharaman, Michael Requa, Ryan Kastner. 1-8 [doi]
• Hierarchical reconfiguration of FPGAsDirk Koch, Christian Beckhoff. 1-8 [doi]
• FPGA implementation of an interior point method for high-speed model predictive controlJunyi Liu, Helfried Peyrl, Andreas Burg, George A. Constantinides. 1-8 [doi]
• Efficient implementation of a single-precision floating-point arithmetic unit on FPGAWilson Jose, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias. 1-4 [doi]
• Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architecturesGhada Dessouky, Michael Klaiber, Donald G. Bailey, Sven Simon. 1-8 [doi]
• Run-time power gating in hybrid ARM-FPGA devicesMohammad Hosseinabady, Jose Luis Nunez-Yanez. 1-6 [doi]
• Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical securityEmna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez. 1-4 [doi]
• Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technologyHonlian Su, Yu Fujita, Hideharu Amano. 1-6 [doi]
• High-precision self-characterization for the LUT burn-in information leakage threatKenneth M. Zick, Sen Li, Matthew French. 1-6 [doi]
• Portable module relocation and bitstream compression for Xilinx FPGAsChristian Beckhoff, Dirk Koch, Jim Torresen. 1-8 [doi]
• A design support tool set for asynchronous circuits with bundled-data implementation on FPGAsKeitaro Takizawa, Shunya Hosaka, Hiroshi Saito. 1-4 [doi]
• MAPC: Memory access pattern based controllerTassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero. 1-4 [doi]
• Robust and flexible FPGA-based digital PUFTeng Xu, Miodrag Potkonjak. 1-6 [doi]
• DyRACT: A partial reconfiguration enabled accelerator and test platformKizheppatt Vipin, Suhaib A. Fahmy. 1-7 [doi]
• A logic cell architecture exploiting the shannon expansion for the reduction of configuration memoryQian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 1-6 [doi]