FPGA acceleration of SAT/Max-SAT solving using variable-way cache

Kenji Kanazawa, Tsutomu Maruyama. FPGA acceleration of SAT/Max-SAT solving using variable-way cache. In 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014. pages 1-4, IEEE, 2014. [doi]

Abstract

Abstract is missing.