Abstract is missing.
- rrBox: A remote dynamically reconfigurable network processing middleboxTze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono. 1-4 [doi]
- A scalable pipelined architecture for biomimetic vision sensorsDaniel Llamocca, Brian K. Dean. 1-6 [doi]
- Power-efficient range-match-based packet classification on FPGAYun R. Qu, Viktor K. Prasanna. 1-8 [doi]
- An FPGA implementation of a phylogenetic tree reconstruction algorithm using an alternative second-pass optimizationHenry Block, Tsutomu Maruyama. 1-4 [doi]
- An LZ77-style bit-level compression for trace data compactionKai-Uwe Irrgang, Thomas B. Preußer. 1-4 [doi]
- A study of data partitioning on OpenCL-based FPGAsZe-ke Wang, Bingsheng He, Wei Zhang. 1-8 [doi]
- FPGA-based all-digital transmittersRui Fiel Cordeiro, Arnaldo S. R. Oliveira, José M. N. Vieira. 1-2 [doi]
- Energy optimization of FPGA-based stream-oriented computing with power gatingMohammad Hosseinabady, Jose Luis Nunez-Yanez. 1-6 [doi]
- NetFPGA - rapid prototyping of high bandwidth devices in open sourceNoa Zilberman, Yury Audzevich, Georgina Kalogeridou, Neelakandan Manihatty Bojan, Jingyun Zhang, Andrew W. Moore 0002. 1 [doi]
- Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directionsMeena Belwal, Madhura Purnaprajna, T. S. B. Sudarshan. 1-8 [doi]
- A variable length hash method for faster short read mapping on FPGAYoko Sogabe, Tsutomu Maruyama. 1-6 [doi]
- Data protection using recursive inverse functionTeng Xu, Hongxiang Gu, Miodrag Potkonjak. 1-4 [doi]
- FPGA implementation to estimate the number of endmembers in hyperspectral imagesCarlos González, Daniel Mozos, Sebastiaá López, Roberto Sarmiento. 1-8 [doi]
- Hoplite: Building austere overlay NoCs for FPGAsNachiket Kapre, Jan Gray. 1-8 [doi]
- Rapid prototyping and Design Space Exploration methodologies for many-accelerator systemsEfstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris. 1-2 [doi]
- Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platformYaman Umuroglu, Donn Morrison, Magnus Jahre. 1-8 [doi]
- A software configurable coprocessor-based state-space controllerAaron Mills, Pei Zhang, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones. 1-6 [doi]
- A rapid prototyping framework for nano-photonic acceleratorsWolfgang Buter, Alberto García Ortiz, A. Ali, S. Mahmood, S. Arefin, V. V. Parsi Sreenivas, R. B. Bergman. 1-4 [doi]
- Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flowJin-Hee Kim, Jason H. Anderson. 1-8 [doi]
- Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAsYuan Xue, Patrick Cronin, Chengmo Yang, Jingtong Hu. 1-8 [doi]
- Ultra low latency dataflow rendererSebastian Friston, Anthony Steed, Simon Tilbury, Georgi Gaydadjiev. 1-4 [doi]
- Parallel feature extraction and heterogeneous object-detection for multi-camera driver assistance systemsStefan Wonneberger, Peter Muehlfellner, Pedro Ceriotti, Thorsten Graf, Rolf Ernst. 1-4 [doi]
- Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarksOleg Petelin, Vaughn Betz. 1-4 [doi]
- Optimizing energy efficient low-swing interconnect for sub-threshold FPGAsHe Qi, Oluseyi A. Ayorinde, Yu Huang, Benton H. Calhoun. 1-4 [doi]
- Building a distributed key-value store with FPGA-based microserversZsolt István, David Sidler, Gustavo Alonso. 1 [doi]
- s - An analysis tool, method and framework for advanced measurements and reliability assessments on modern nanoscale FPGAsPetr Pfeifer. 1 [doi]
- Data-triggered breakpoint for in-circuit debug without re-implementationYutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura. 1-4 [doi]
- 7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano. 1 [doi]
- Accurate power analysis for near-Vt RRAM-based FPGAXifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 1-4 [doi]
- A run time interpretation approach for creating custom acceleratorsSen Ma, Zeyad Aklah, David L. Andrews. 1-4 [doi]
- Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inferenceSkand Hurkat, Jungwook Choi, Eriko Nurvitadhi, Jose F. Martinez, Rob A. Rutenbar. 1-8 [doi]
- Hybrid FPGA debug approachZdravko Panjkov, Andreas Wasserbauer, Timm Ostermann, Richard Hagelauer. 1-8 [doi]
- An efficient many-core architecture for Elliptic Curve Cryptography security assessmentMarco Indaco, Fabio Lauri, Andrea Miele, Pascal Trotta. 1-6 [doi]
- Efficient assembly for high order unstructured FEM meshesPavel Burovskiy, Paul Grigoras, Spencer J. Sherwin, Wayne Luk. 1-6 [doi]
- Static hardware task placement on multi-context FPGA using hybrid genetic algorithmHao Liang, Sharad Sinha, Rakesh Warrier, Wei Zhang. 1-8 [doi]
- A resilient, flash-free soft error mitigation concept for the CBM-ToF read-out chain via GBT-SCAAndrei-Dumitru Oancea, Christian Stüllein, Jano Gebelein, Udo Kebschull. 1-4 [doi]
- Serial and parallel interleaved modular multipliers on FPGA platformKhalid Javeed, Xiaojun Wang, Mike Scott. 1-4 [doi]
- Enhancing stochastic computations via process variationRui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto. 1-7 [doi]
- Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industryEddie Hung. 1-4 [doi]
- High-level FPGA logic synthesis from .NET programs for software developersZoltan Lehoczky, Richard Toth, Krisztian Somogyi. 1 [doi]
- Placing partially reconfigurable stream processing applications on FPGAsNicolae Bogdan Grigore, Dirk Koch. 1-4 [doi]
- Domain-specific optimisation for the high-level synthesis of CellML-based simulation acceleratorsJulian Oppermann, Andreas Koch 0001, Ting Yu, Oliver Sinnen. 1-7 [doi]
- Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devicesMohammad Hosseinabady, Jose Luis Nunez-Yanez. 1-6 [doi]
- High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAsDionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios, Dimitrios Soudris. 1-2 [doi]
- A scalable FPGA architecture for nonnegative least squares problemsAlric Althoff, Ryan Kastner. 1-8 [doi]
- OpenCL computing on FPGA using multiportedShared Memory, Tahsin Turker Mutlugun, Sheng-De Wang. 1-4 [doi]
- Automatic support for multi-module parallelism from computational patternsNithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne. 1-8 [doi]
- Efficient data-stream management for shared-memory many-core systemsNuno Neves, Pedro Tomás, Nuno Roma. 1-8 [doi]
- Estimating circuit delays in FPGAs after technology mappingBerg Severens, Elias Vansteenkiste, Karel Heyse, Dirk Stroobandt. 1-4 [doi]
- A scalable architecture for multi-class visual object detectionSiddharth Advani, Yasuki Tanabe, Kevin M. Irick, Jack Sampson, Vijaykrishnan Narayanan. 1-8 [doi]
- Over effective hard real-time hardware tasks scheduling and allocationZakarya Guettatfi, Omar Kermia, Abdelhakim Khouas. 1-2 [doi]
- SPINE: From C loop-nests to highly efficient accelerators using Algorithmic SpeciesMark Wijtvliet, Shakith Fernando, Henk Corporaal. 1-6 [doi]
- Temperature-triggered behavioral IPs HW Trojan detection method with FPGAsXiaotong Li, Benjamin Carrión Schafer. 1-4 [doi]
- FPGA-based all-digital Software Defined Radio receiverAndre Prata, Arnaldo S. R. Oliveira, Nuno Borges Carvalho. 1-2 [doi]
- Limits of FPGA acceleration of 3D Green's Function computation for geophysical applicationsNachiket Kapre, Jayakrishnan Selva Kumar, Parjanya Gupta, Sagar Shrishailappa Masuti, Sylvain Barbot. 1-8 [doi]
- An automated technique to generate relocatable partial bitstreams for Xilinx FPGAsRoel Oomen, Tuan D. A. Nguyen, Akash Kumar, Henk Corporaal. 1-4 [doi]
- Scavenger: Automating the construction of application-optimized memory hierarchiesHsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer. 1-8 [doi]
- SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systemsZeping Xue, David B. Thomas. 1-7 [doi]
- Reduction calculator in an FPGA based switching Hub for high performance clustersTakuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano. 1-4 [doi]
- PushPush: Seamless integration of hardware and software objects via function calls over AXIShane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica. 1-8 [doi]
- Ultra-fast NoC emulation on a single FPGAThiem Van Chu, Shimpei Sato, Kenji Kise. 1-8 [doi]
- UniStream: A unified stream architecture combining configuration and data processingJian Yan, Jifang Jin, Ying Wang, Xuegong Zhou, Philip Leong, Lingli Wang. 1-4 [doi]
- Variable-latency signed addition on FPGAsAlessandro Cilardo. 1-6 [doi]
- A deep convolutional neural network based on nested residue number systemHiroki Nakahara, Tsutomu Sasao. 1-6 [doi]
- Automatic generation of high throughput energy efficient streaming architectures for arbitrary fixed permutationsRen Chen, Viktor K. Prasanna. 1-8 [doi]
- A framework for integrated monitoring of real-time embedded SoCGiacomo Valente. 1-2 [doi]
- m)Zia Uddin Ahamed Khan, Mohammed Benaissa. 1-6 [doi]
- Adaptive MRAM-based CGRAsXiaobin Liu, Tedy Thomas, Alan Boguslawski, Russell Tessier. 1-4 [doi]
- Generating FPGA accelerators for chemical similarity assessmentNikolaos Alachiotis. 1-4 [doi]
- Using island-style bi-directional intra-CLB routing in low-power FPGAsOluseyi A. Ayorinde, He Qi, Yu Huang, Benton H. Calhoun. 1-7 [doi]
- Pipelined NoC router architecture design with buffer configuration exploration on FPGAQi Chen, Qiang Liu. 1-4 [doi]
- CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computingGabriel Weisz, James C. Hoe. 1-8 [doi]
- Characterisation of feasibility regions in FPGAs under adaptive DVFSNizar Dahir, Pedro B. Campos, Gianluca Tempesti, Martin Trefzer, Andrew M. Tyrrell. 1-4 [doi]
- Fast FPGA system for microarchitecture optimization on synthesizable modern processor designLibo Huang, Yongwen Wang, Qiang Dou, Chengyi Zhang, Caixia Sun, Chao Xu. 1-4 [doi]
- Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-ChipEdoardo Fusella, Alessandro Cilardo, Antonino Mazzeo. 1-2 [doi]
- Compact dual block AES core on FPGA for CCM ProtocolJoão Carlos Resende, Ricardo Chaves. 1-8 [doi]
- Towards efficient discrete Gaussian sampling for lattice-based cryptographyChaohui Du, Guoqiang Bai. 1-6 [doi]
- Design and simulation tools for Embedded NOCs on FPGAsMohamed S. Abdelfattah, Andrew Bitar, Ange Yaghi, Vaughn Betz. 1 [doi]
- A transport-layer network for distributed FPGA platformsSang-Woo Jun, Ming Liu, Shuotao Xu, Arvind. 1-4 [doi]
- Towards heterogeneous solvers for large-scale linear systemsStylianos I. Venieris, Grigorios Mingas, Christos-Savvas Bouganis. 1-8 [doi]
- Inter-procedural resource sharing in High Level Synthesis through function proxiesMarco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi. 1-8 [doi]
- A technology mapper for depth-constrained FPGA logic cellsZhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne. 1-8 [doi]
- ParaLaR: A parallel FPGA router based on Lagrangian relaxationChin Hau Hoo, Akash Kumar, Yajun Ha. 1-6 [doi]
- In-field vulnerability analysis of hardware-accelerated computer vision applicationsI. Chadjiminas, Christos Kyrkou, Theocharis Theocharides, Maria K. Michael, Christos Ttofis. 1-4 [doi]
- Recursive pipelined genetic propagation for bilevel optimisationShengjia Shao, Liucheng Guo, Ce Guo, Thomas C. P. Chau, David B. Thomas, Wayne Luk, Stephen Weston. 1-6 [doi]
- A fully pipelined kernel normalised least mean squares processor for accelerated parameter optimisationNicholas J. Fraser, Duncan J. M. Moss, Junkyu Lee, Stephen Tridgell, Craig T. Jin, Philip H. W. Leong. 1-6 [doi]
- FPGA based nonlinear Support Vector Machine training using an ensemble learningMudhar Bin Rabieah, Christos-Savvas Bouganis. 1-4 [doi]
- Hierarchical library based power estimator for versatile FPGAsHao Liang, Wei Zhang, Sharad Sinha, Yi-Chung Chen, Hai Li. 1 [doi]
- PrefacePeter Y. K. Cheung, Wayne Luk, Cristina Silvano. 1-2 [doi]
- A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAsStefano Di Carlo, Paolo Prinetto, Pascal Trotta, Jan Andersson. 1-4 [doi]
- Towards a guided design flow for heterogeneous reconfigurable architecturesTimm Bostelmann, Sergei Sawitzki. 1-2 [doi]
- Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAsAli Ahari, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. 1-6 [doi]
- From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesisJoão Andrade, Nithin George, Kimon Karras, David Novo, Vitor Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes. 1-8 [doi]
- Software-in-the-Loop simulation of embedded control applications based on Virtual PlatformsStephan Werner 0002, Leonard Masing, Fabian Lesniak, Jürgen Becker. 1-8 [doi]
- FPGA-based all-digital software defined radio system demonstrationRui Fiel Cordeiro, Andre Prata, Arnaldo S. R. Oliveira, Nuno Borges Carvalho, José M. N. Vieira. 1 [doi]
- An efficient reconfigurable architecture by characterizing most frequent logic functionsIman Ahmadpour, Behnam Khaleghi, Hossein Asadi. 1-6 [doi]
- Greedy approach based heuristics for partitioning SpMxV on FPGAsJiasen Huang, Weina Lu, Junyan Ren. 1-2 [doi]
- Significant papers from the first 25 years of the FPL conferencePhilip H. W. Leong, Hideharu Amano, Jason Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, Junkyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang. 1-3 [doi]