A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA

Henry Block, Tsutomu Maruyama. A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA. In 2013 International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, December 9-11, 2013. pages 318-321, IEEE, 2013. [doi]

Abstract

Abstract is missing.